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| author |   Andrew Opalach <andrew@akon.city>
| 2019-04-13 12:40:52 -0400 |
|---|---|---|
| committer | Andrew Opalach <andrew@akon.city>
| 2019-04-13 12:40:52 -0400 |
| commit | 55bfff7cf6541caac172b43186cf14405185b14d (patch) | |
| tree | c1ae99d2b39f8df8933d81ec2e61e81050bdb410 /frontends/calculator/CEdev/lib/shared | |
| parent | 761462861fc1228e65546c4e0f877d5212320082 (diff) | |
| download | cetris-55bfff7cf6541caac172b43186cf14405185b14d.tar.gz cetris-55bfff7cf6541caac172b43186cf14405185b14d.tar.bz2 cetris-55bfff7cf6541caac172b43186cf14405185b14d.zip | |
fix curses on linux
Diffstat (limited to 'frontends/calculator/CEdev/lib/shared')
204 files changed, 5462 insertions, 5462 deletions
diff --git a/frontends/calculator/CEdev/lib/shared/abort.src b/frontends/calculator/CEdev/lib/shared/abort.src index b2d9648..cbab8af 100644 --- a/frontends/calculator/CEdev/lib/shared/abort.src +++ b/frontends/calculator/CEdev/lib/shared/abort.src @@ -1,13 +1,13 @@ -; --- -; triggers open debugger -; --- - - .def _abort - .ref __exit - .assume adl=1 - -_abort: - scf - sbc hl,hl - ld (hl),1 - jp __exit +; ---
+; triggers open debugger
+; ---
+
+ .def _abort
+ .ref __exit
+ .assume adl=1
+
+_abort:
+ scf
+ sbc hl,hl
+ ld (hl),1
+ jp __exit
diff --git a/frontends/calculator/CEdev/lib/shared/abs.src b/frontends/calculator/CEdev/lib/shared/abs.src index 5dc8aa1..65aa2b6 100644 --- a/frontends/calculator/CEdev/lib/shared/abs.src +++ b/frontends/calculator/CEdev/lib/shared/abs.src @@ -1,17 +1,17 @@ - .def _abs - .assume adl=1 - -;int abs(int); - -_abs: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - sbc hl,de - ret p - ex de,hl - ret - + .def _abs
+ .assume adl=1
+
+;int abs(int);
+
+_abs:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ sbc hl,de
+ ret p
+ ex de,hl
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/atoi.src b/frontends/calculator/CEdev/lib/shared/atoi.src index 2619388..86bc88e 100644 --- a/frontends/calculator/CEdev/lib/shared/atoi.src +++ b/frontends/calculator/CEdev/lib/shared/atoi.src @@ -1,22 +1,22 @@ - .ref _strtol - .def _atoi - .assume adl=1 - -; int atoi(char *cp); - -_atoi: - pop bc - pop de - push de - push bc - ld bc,10 - push bc - ld c,b - push bc - push de - call _strtol - pop de - pop bc - pop bc - ret - + .ref _strtol
+ .def _atoi
+ .assume adl=1
+
+; int atoi(char *cp);
+
+_atoi:
+ pop bc
+ pop de
+ push de
+ push bc
+ ld bc,10
+ push bc
+ ld c,b
+ push bc
+ push de
+ call _strtol
+ pop de
+ pop bc
+ pop bc
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/atol.src b/frontends/calculator/CEdev/lib/shared/atol.src index 7bf22d7..b241ad7 100644 --- a/frontends/calculator/CEdev/lib/shared/atol.src +++ b/frontends/calculator/CEdev/lib/shared/atol.src @@ -1,8 +1,8 @@ - .ref _atoi - .def _atol - .assume adl=1 - -; long atol(char *cp); - -_atol equ _atoi - + .ref _atoi
+ .def _atol
+ .assume adl=1
+
+; long atol(char *cp);
+
+_atol equ _atoi
+
diff --git a/frontends/calculator/CEdev/lib/shared/atomic_load_32.src b/frontends/calculator/CEdev/lib/shared/atomic_load_32.src index a49df22..d0bb9fa 100644 --- a/frontends/calculator/CEdev/lib/shared/atomic_load_32.src +++ b/frontends/calculator/CEdev/lib/shared/atomic_load_32.src @@ -1,61 +1,61 @@ -; --- -; uint32_t atomic_load_32(volatile uint32_t *p) -; --- - - .def _atomic_load_32 - .assume adl=1 - -_atomic_load_32: - pop hl - ex (sp),iy - push hl - ld c,0 -retry: -; Wait for a different (increasing) amount of time before each retry to prevent -; getting caught in an endless loop of the value changing between reads with a -; fixed period equal to the amount of time it takes for each retry - inc c - ld b,c -wait: - djnz wait -; Read the value twice. - lea hl,iy+3 - ; Time between first and last byte read: - ld de,(iy) ; 2R - ld a,(hl) ; + 1F+1R - cp a,(hl) ; + 1F+1R - ld hl,(iy) ; + 3F+3R - ; = 5F+7R - ; = 48cc (assuming F = R = 3) - ; = 1us (assuming 48MHz clock speed) - ; Don't need to worry about DMA, just - ; retry until not interrupted by DMA -; Retry if the values read differ. -; -; If the values differ, then the underlying value changed between reading the -; first byte of the first 32-bit read and the last byte of the second 32-bit -; read: -; * If a change occurs between the two 32-bit reads, then both values read -; remain valid. -; * If a change occurs in the middle of one of the 32-bit reads: -; * If the bytes already read change but the bytes yet to read do not -; change, then the value read is the valid value before the change. -; * If the bytes already read do not change but the yet still to read -; change, then the value read is the valid value after the change. -; * If the bytes already read and the bytes yet to read change, then the -; value read is an invalid mix of the values before and after the change. -; -; Without reading the value again, there is not enough information to determine -; if the third case occurred. If it did occur, then one of the values is -; invalid. But there is also not enough information to determine which is -; invalid, and therefore which is valid. So reading the value must be retried. -; -; (Furthermore, if a change occurs in the middle of both 32-bit reads and the -; bytes already read change in both, then both values read become invalid.) - jr nz,retry - sbc hl,de - jr nz,retry -; Values don't differ, good to go. - add hl,de - ld e,a ; euhl = value read - ret +; ---
+; uint32_t atomic_load_32(volatile uint32_t *p)
+; ---
+
+ .def _atomic_load_32
+ .assume adl=1
+
+_atomic_load_32:
+ pop hl
+ ex (sp),iy
+ push hl
+ ld c,0
+retry:
+; Wait for a different (increasing) amount of time before each retry to prevent
+; getting caught in an endless loop of the value changing between reads with a
+; fixed period equal to the amount of time it takes for each retry
+ inc c
+ ld b,c
+wait:
+ djnz wait
+; Read the value twice.
+ lea hl,iy+3
+ ; Time between first and last byte read:
+ ld de,(iy) ; 2R
+ ld a,(hl) ; + 1F+1R
+ cp a,(hl) ; + 1F+1R
+ ld hl,(iy) ; + 3F+3R
+ ; = 5F+7R
+ ; = 48cc (assuming F = R = 3)
+ ; = 1us (assuming 48MHz clock speed)
+ ; Don't need to worry about DMA, just
+ ; retry until not interrupted by DMA
+; Retry if the values read differ.
+;
+; If the values differ, then the underlying value changed between reading the
+; first byte of the first 32-bit read and the last byte of the second 32-bit
+; read:
+; * If a change occurs between the two 32-bit reads, then both values read
+; remain valid.
+; * If a change occurs in the middle of one of the 32-bit reads:
+; * If the bytes already read change but the bytes yet to read do not
+; change, then the value read is the valid value before the change.
+; * If the bytes already read do not change but the yet still to read
+; change, then the value read is the valid value after the change.
+; * If the bytes already read and the bytes yet to read change, then the
+; value read is an invalid mix of the values before and after the change.
+;
+; Without reading the value again, there is not enough information to determine
+; if the third case occurred. If it did occur, then one of the values is
+; invalid. But there is also not enough information to determine which is
+; invalid, and therefore which is valid. So reading the value must be retried.
+;
+; (Furthermore, if a change occurs in the middle of both 32-bit reads and the
+; bytes already read change in both, then both values read become invalid.)
+ jr nz,retry
+ sbc hl,de
+ jr nz,retry
+; Values don't differ, good to go.
+ add hl,de
+ ld e,a ; euhl = value read
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/atomic_load_decreasing_32.src b/frontends/calculator/CEdev/lib/shared/atomic_load_decreasing_32.src index 639eac1..555e93e 100644 --- a/frontends/calculator/CEdev/lib/shared/atomic_load_decreasing_32.src +++ b/frontends/calculator/CEdev/lib/shared/atomic_load_decreasing_32.src @@ -1,89 +1,89 @@ -; --- -; uint32_t atomic_load_decreasing_32(volatile uint32_t *p) -; --- - - .def _atomic_load_decreasing_32 - .assume adl=1 - -_atomic_load_decreasing_32: - pop hl - ex (sp),iy - push hl -; Temporarily disable interrupts. - ld a,i - di -; Read the value twice. -; first value read = cude, second value read = auhl - ; Time between first and last byte read: - ld de,(iy) ; 2R - ld c,(iy+3) ; + 3F+1R - ld hl,(iy) ; + 3F+3R - ld a,(iy+3) ; + 3F+1R - ; = 9F+7R - ; = 56cc (assuming F = R = 3) - ; ~ 1.17us (assuming 48MHz clock speed) - ; + approximate worst-case LCD + USB DMA - ; ~ 5us -; Re-enable interrupts if they were previously enabled. - jp po,no_ei - ei -no_ei: -; Compare and return the greater of the two values read. -; -; If the values differ, then the underlying value changed between reading the -; first byte of the first 32-bit read and the last byte of the second 32-bit -; read: -; * If a change occurs between the two 32-bit reads, then both values read -; remain valid. -; * If a change occurs in the middle of one of the 32-bit reads: -; * If the bytes already read change but the bytes yet to read do not -; change, then the value read is the valid value before the change. -; * If the bytes already read do not change but the yet still to read -; change, then the value read is the valid value after the change. -; * If the bytes already read and the bytes yet to read change, then the -; value read is an invalid mix of the values before and after the change. -; -; If the final case did not occur, then both values read are valid. -; -; If the final case occurred for only the second value read, then due to reading -; bytes in little-endian order, one to three upper bytes will reflect the -; decreased value after the change. Regardless of the lower bytes, the valid, -; first value read will be greater than the invalid, second value read. -; -; If the final case occurred for only the first value read, then due to reading -; bytes in little-endian order, one to three upper bytes will reflect the -; decreased value after the change, while the remaining one to three lower bytes -; will reflect the value before the change. If it is assumed that the value -; decreased by less than 256, then the upper bytes must have decreased through -; borrow and the lower bytes of the valid, second value read will be greater -; than the lower bytes of the invalid, first value read. And because the full -; second value read will reflect the the decreased value after the change, and -; therefore the two values read will only differ in the lower bytes, it follows -; that the full, valid, second valid read will be greater than the full, -; invalid, first value read. (Note that this assertion can be extended to -; include 256 because only one byte would change, making this whole case -; unreachable.) -; -; If the third case occurred for both values read, then both are invalid. There -; is no reasonable way to detect this, so it is assumed that this did not occur. -; -; Combining all of these cases and assumptions, the greater of the two values -; read will always be valid. - or a,a - sbc hl,de - sbc a,c ; auhl = second value read - ; - first value read - jr c,swap -; second value read >= first value read -; ==> second value read is valid - add hl,de - adc a,c - ld e,a ; euhl = second value read - ret - -swap: -; second value read < first value read -; ==> first value read is valid - ex de,hl - ld e,c ; euhl = first value read - ret +; ---
+; uint32_t atomic_load_decreasing_32(volatile uint32_t *p)
+; ---
+
+ .def _atomic_load_decreasing_32
+ .assume adl=1
+
+_atomic_load_decreasing_32:
+ pop hl
+ ex (sp),iy
+ push hl
+; Temporarily disable interrupts.
+ ld a,i
+ di
+; Read the value twice.
+; first value read = cude, second value read = auhl
+ ; Time between first and last byte read:
+ ld de,(iy) ; 2R
+ ld c,(iy+3) ; + 3F+1R
+ ld hl,(iy) ; + 3F+3R
+ ld a,(iy+3) ; + 3F+1R
+ ; = 9F+7R
+ ; = 56cc (assuming F = R = 3)
+ ; ~ 1.17us (assuming 48MHz clock speed)
+ ; + approximate worst-case LCD + USB DMA
+ ; ~ 5us
+; Re-enable interrupts if they were previously enabled.
+ jp po,no_ei
+ ei
+no_ei:
+; Compare and return the greater of the two values read.
+;
+; If the values differ, then the underlying value changed between reading the
+; first byte of the first 32-bit read and the last byte of the second 32-bit
+; read:
+; * If a change occurs between the two 32-bit reads, then both values read
+; remain valid.
+; * If a change occurs in the middle of one of the 32-bit reads:
+; * If the bytes already read change but the bytes yet to read do not
+; change, then the value read is the valid value before the change.
+; * If the bytes already read do not change but the yet still to read
+; change, then the value read is the valid value after the change.
+; * If the bytes already read and the bytes yet to read change, then the
+; value read is an invalid mix of the values before and after the change.
+;
+; If the final case did not occur, then both values read are valid.
+;
+; If the final case occurred for only the second value read, then due to reading
+; bytes in little-endian order, one to three upper bytes will reflect the
+; decreased value after the change. Regardless of the lower bytes, the valid,
+; first value read will be greater than the invalid, second value read.
+;
+; If the final case occurred for only the first value read, then due to reading
+; bytes in little-endian order, one to three upper bytes will reflect the
+; decreased value after the change, while the remaining one to three lower bytes
+; will reflect the value before the change. If it is assumed that the value
+; decreased by less than 256, then the upper bytes must have decreased through
+; borrow and the lower bytes of the valid, second value read will be greater
+; than the lower bytes of the invalid, first value read. And because the full
+; second value read will reflect the the decreased value after the change, and
+; therefore the two values read will only differ in the lower bytes, it follows
+; that the full, valid, second valid read will be greater than the full,
+; invalid, first value read. (Note that this assertion can be extended to
+; include 256 because only one byte would change, making this whole case
+; unreachable.)
+;
+; If the third case occurred for both values read, then both are invalid. There
+; is no reasonable way to detect this, so it is assumed that this did not occur.
+;
+; Combining all of these cases and assumptions, the greater of the two values
+; read will always be valid.
+ or a,a
+ sbc hl,de
+ sbc a,c ; auhl = second value read
+ ; - first value read
+ jr c,swap
+; second value read >= first value read
+; ==> second value read is valid
+ add hl,de
+ adc a,c
+ ld e,a ; euhl = second value read
+ ret
+
+swap:
+; second value read < first value read
+; ==> first value read is valid
+ ex de,hl
+ ld e,c ; euhl = first value read
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/atomic_load_increasing_32.src b/frontends/calculator/CEdev/lib/shared/atomic_load_increasing_32.src index d8c871f..1ef6f8f 100644 --- a/frontends/calculator/CEdev/lib/shared/atomic_load_increasing_32.src +++ b/frontends/calculator/CEdev/lib/shared/atomic_load_increasing_32.src @@ -1,88 +1,88 @@ -; --- -; uint32_t atomic_load_increasing_32(volatile uint32_t *p) -; --- - - .def _atomic_load_increasing_32 - .assume adl=1 - -_atomic_load_increasing_32: - pop hl - ex (sp),iy - push hl -; Temporarily disable interrupts. - ld a,i - di -; Read the value twice. -; first value read = cude, second value read = auhl - ; Time between first and last byte read: - ld de,(iy) ; 2R - ld c,(iy+3) ; + 3F+1R - ld hl,(iy) ; + 3F+3R - ld a,(iy+3) ; + 3F+1R - ; = 9F+7R - ; = 56cc (assuming F = R = 3) - ; ~ 1.17us (assuming 48MHz clock speed) - ; + approximate worst-case LCD + USB DMA - ; ~ 5us -; Re-enable interrupts if they were previously enabled. - jp po,no_ei - ei -no_ei: -; Compare and return the lesser of the two values read. -; -; If the values differ, then the underlying value changed between reading the -; first byte of the first 32-bit read and the last byte of the second 32-bit -; read: -; * If a change occurs between the two 32-bit reads, then both values read -; remain valid. -; * If a change occurs in the middle of one of the 32-bit reads: -; * If the bytes already read change but the bytes yet to read do not -; change, then the value read is the valid value before the change. -; * If the bytes already read do not change but the yet still to read -; change, then the value read is the valid value after the change. -; * If the bytes already read and the bytes yet to read change, then the -; value read is an invalid mix of the values before and after the change. -; -; If the final case did not occur, then both values read are valid. -; -; If the final case occurred for only the second value read, then due to reading -; bytes in little-endian order, one to three upper bytes will reflect the -; increased value after the change. Regardless of the lower bytes, the valid, -; first value read will be less than the invalid, second value read. -; -; If the final case occurred for only the first value read, then due to reading -; bytes in little-endian order, one to three upper bytes will reflect the -; increased value after the change, while the remaining one to three lower bytes -; will reflect the value before the change. If it is assumed that the value -; increased by less than 256, then the upper bytes must have increased through -; carry and the lower bytes of the valid, second value read will be less than -; the lower bytes of the invalid, first value read. And because the full second -; value read will reflect the the increased value after the change, and -; therefore the two values read will only differ in the lower bytes, it follows -; that the full, valid, second valid read will be less than the full, invalid, -; first value read. (Note that this assertion can be extended to include 256 -; because only one byte would change, making this whole case unreachable.) -; -; If the third case occurred for both values read, then both are invalid. There -; is no reasonable way to detect this, so it is assumed that this did not occur. -; -; Combining all of these cases and assumptions, the lesser of the two values -; read will always be valid. - or a,a - sbc hl,de - sbc a,c ; auhl = second value read - ; - first value read - jr c,no_swap -; second value read >= first value read -; ==> first value read is valid - ex de,hl - ld e,c ; euhl = first value read - ret - -no_swap: -; second value read < first value read -; ==> second value read is valid - add hl,de - adc a,c - ld e,a ; euhl = second value read - ret +; ---
+; uint32_t atomic_load_increasing_32(volatile uint32_t *p)
+; ---
+
+ .def _atomic_load_increasing_32
+ .assume adl=1
+
+_atomic_load_increasing_32:
+ pop hl
+ ex (sp),iy
+ push hl
+; Temporarily disable interrupts.
+ ld a,i
+ di
+; Read the value twice.
+; first value read = cude, second value read = auhl
+ ; Time between first and last byte read:
+ ld de,(iy) ; 2R
+ ld c,(iy+3) ; + 3F+1R
+ ld hl,(iy) ; + 3F+3R
+ ld a,(iy+3) ; + 3F+1R
+ ; = 9F+7R
+ ; = 56cc (assuming F = R = 3)
+ ; ~ 1.17us (assuming 48MHz clock speed)
+ ; + approximate worst-case LCD + USB DMA
+ ; ~ 5us
+; Re-enable interrupts if they were previously enabled.
+ jp po,no_ei
+ ei
+no_ei:
+; Compare and return the lesser of the two values read.
+;
+; If the values differ, then the underlying value changed between reading the
+; first byte of the first 32-bit read and the last byte of the second 32-bit
+; read:
+; * If a change occurs between the two 32-bit reads, then both values read
+; remain valid.
+; * If a change occurs in the middle of one of the 32-bit reads:
+; * If the bytes already read change but the bytes yet to read do not
+; change, then the value read is the valid value before the change.
+; * If the bytes already read do not change but the yet still to read
+; change, then the value read is the valid value after the change.
+; * If the bytes already read and the bytes yet to read change, then the
+; value read is an invalid mix of the values before and after the change.
+;
+; If the final case did not occur, then both values read are valid.
+;
+; If the final case occurred for only the second value read, then due to reading
+; bytes in little-endian order, one to three upper bytes will reflect the
+; increased value after the change. Regardless of the lower bytes, the valid,
+; first value read will be less than the invalid, second value read.
+;
+; If the final case occurred for only the first value read, then due to reading
+; bytes in little-endian order, one to three upper bytes will reflect the
+; increased value after the change, while the remaining one to three lower bytes
+; will reflect the value before the change. If it is assumed that the value
+; increased by less than 256, then the upper bytes must have increased through
+; carry and the lower bytes of the valid, second value read will be less than
+; the lower bytes of the invalid, first value read. And because the full second
+; value read will reflect the the increased value after the change, and
+; therefore the two values read will only differ in the lower bytes, it follows
+; that the full, valid, second valid read will be less than the full, invalid,
+; first value read. (Note that this assertion can be extended to include 256
+; because only one byte would change, making this whole case unreachable.)
+;
+; If the third case occurred for both values read, then both are invalid. There
+; is no reasonable way to detect this, so it is assumed that this did not occur.
+;
+; Combining all of these cases and assumptions, the lesser of the two values
+; read will always be valid.
+ or a,a
+ sbc hl,de
+ sbc a,c ; auhl = second value read
+ ; - first value read
+ jr c,no_swap
+; second value read >= first value read
+; ==> first value read is valid
+ ex de,hl
+ ld e,c ; euhl = first value read
+ ret
+
+no_swap:
+; second value read < first value read
+; ==> second value read is valid
+ add hl,de
+ adc a,c
+ ld e,a ; euhl = second value read
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/atos.src b/frontends/calculator/CEdev/lib/shared/atos.src index cb3403b..6c39f89 100644 --- a/frontends/calculator/CEdev/lib/shared/atos.src +++ b/frontends/calculator/CEdev/lib/shared/atos.src @@ -1,8 +1,8 @@ - .ref _atoi - .def _atos - .assume adl=1 - -; short int atos(char *cp); - -_atos equ _atoi - + .ref _atoi
+ .def _atos
+ .assume adl=1
+
+; short int atos(char *cp);
+
+_atos equ _atoi
+
diff --git a/frontends/calculator/CEdev/lib/shared/bdivs.src b/frontends/calculator/CEdev/lib/shared/bdivs.src index 1bd30b8..710ad7e 100644 --- a/frontends/calculator/CEdev/lib/shared/bdivs.src +++ b/frontends/calculator/CEdev/lib/shared/bdivs.src @@ -1,44 +1,44 @@ -; (c) Copyright 2001-2008 Zilog Inc. -;------------------------------------------------------------------------- -; Signed Byte Division. -; Input: -; Operand1: -; B : 8 bit dividend (numerator) -; -; Operand2: -; C : 8 bit divisor (denominator) -; -; Output: -; Result: A : 8 bit quotient -; Registers Used: -; d, e -;------------------------------------------------------------------------- - .ref __bdivu - .def __bdivs - .assume adl=1 - -__bdivs: - push bc - xor a,a - sub a,b - jp m,_L0 - ld b,a -_L0: - xor a,a - sub a,c - jp m,_L1 - ld c,a -_L1: - call __bdivu - pop bc - push hl - ld l,a - ld a,b - xor a,c - ld a,l - jp p,_L2 - neg -_L2: - pop hl - ret - +; (c) Copyright 2001-2008 Zilog Inc.
+;-------------------------------------------------------------------------
+; Signed Byte Division.
+; Input:
+; Operand1:
+; B : 8 bit dividend (numerator)
+;
+; Operand2:
+; C : 8 bit divisor (denominator)
+;
+; Output:
+; Result: A : 8 bit quotient
+; Registers Used:
+; d, e
+;-------------------------------------------------------------------------
+ .ref __bdivu
+ .def __bdivs
+ .assume adl=1
+
+__bdivs:
+ push bc
+ xor a,a
+ sub a,b
+ jp m,_L0
+ ld b,a
+_L0:
+ xor a,a
+ sub a,c
+ jp m,_L1
+ ld c,a
+_L1:
+ call __bdivu
+ pop bc
+ push hl
+ ld l,a
+ ld a,b
+ xor a,c
+ ld a,l
+ jp p,_L2
+ neg
+_L2:
+ pop hl
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/bdivu.src b/frontends/calculator/CEdev/lib/shared/bdivu.src index cd2b7d3..68b9d82 100644 --- a/frontends/calculator/CEdev/lib/shared/bdivu.src +++ b/frontends/calculator/CEdev/lib/shared/bdivu.src @@ -1,41 +1,41 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Unsigned Byte Division. -; Input: -; Operand1: -; B : 8 bit dividend (numerator x) -; -; Operand2: -; C : 8 bit divisor (denominator y) -; -; Output: -; Result: A : 8 bit quotient -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __bdivu - .assume adl=1 - -__bdivu: - push bc - push hl - ld h,b - xor a,a - ld b,8 ;i = 8 (bit counter) -loop: - sla h - rla - jr c,over - cp a,c - jr c,under -over: - sub a,c - inc h -under: - djnz loop - - ld a,h - pop hl - pop bc - ret - +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Unsigned Byte Division.
+; Input:
+; Operand1:
+; B : 8 bit dividend (numerator x)
+;
+; Operand2:
+; C : 8 bit divisor (denominator y)
+;
+; Output:
+; Result: A : 8 bit quotient
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __bdivu
+ .assume adl=1
+
+__bdivu:
+ push bc
+ push hl
+ ld h,b
+ xor a,a
+ ld b,8 ;i = 8 (bit counter)
+loop:
+ sla h
+ rla
+ jr c,over
+ cp a,c
+ jr c,under
+over:
+ sub a,c
+ inc h
+under:
+ djnz loop
+
+ ld a,h
+ pop hl
+ pop bc
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/bldix.src b/frontends/calculator/CEdev/lib/shared/bldix.src index 6d3dbf7..dbf7ef0 100644 --- a/frontends/calculator/CEdev/lib/shared/bldix.src +++ b/frontends/calculator/CEdev/lib/shared/bldix.src @@ -1,25 +1,25 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; byte load a,(ix+nnnnnn) -; Input: -; Operand1: -; BC : 24-bit offset from ix -; -; Output: -; Result: A : 8 bit -; -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __bldix - .assume adl=1 - -__bldix: - push ix - push af ; Preserve flags - add ix,bc - pop af ; Restore flags - ld a,(ix) - pop ix - ret - +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; byte load a,(ix+nnnnnn)
+; Input:
+; Operand1:
+; BC : 24-bit offset from ix
+;
+; Output:
+; Result: A : 8 bit
+;
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __bldix
+ .assume adl=1
+
+__bldix:
+ push ix
+ push af ; Preserve flags
+ add ix,bc
+ pop af ; Restore flags
+ ld a,(ix)
+ pop ix
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/bldiy.src b/frontends/calculator/CEdev/lib/shared/bldiy.src index acda08a..3631134 100644 --- a/frontends/calculator/CEdev/lib/shared/bldiy.src +++ b/frontends/calculator/CEdev/lib/shared/bldiy.src @@ -1,17 +1,17 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; byte load a,(iy+nnnnnn) -; Input: -; Operand1: -; BC : 24-bit offset from iy -; -; Output: -; Result: A : 8 bit -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __bldiy - .assume adl=1 - -__bldiy equ 0000FCh +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; byte load a,(iy+nnnnnn)
+; Input:
+; Operand1:
+; BC : 24-bit offset from iy
+;
+; Output:
+; Result: A : 8 bit
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __bldiy
+ .assume adl=1
+
+__bldiy equ 0000FCh
diff --git a/frontends/calculator/CEdev/lib/shared/bmuls.src b/frontends/calculator/CEdev/lib/shared/bmuls.src index 45d7111..1c5ab2e 100644 --- a/frontends/calculator/CEdev/lib/shared/bmuls.src +++ b/frontends/calculator/CEdev/lib/shared/bmuls.src @@ -1,25 +1,25 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Signed Byte Multiply -; Input: -; Operand1: -; A : 8 bit -; -; Operand2: -; B : 8 bit -; -; Output: -; Result: A : 8 bit product -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __bmuls - .assume adl=1 - -__bmuls: - push bc - ld c,a - mlt bc - ld a,c - pop bc - ret +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Signed Byte Multiply
+; Input:
+; Operand1:
+; A : 8 bit
+;
+; Operand2:
+; B : 8 bit
+;
+; Output:
+; Result: A : 8 bit product
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __bmuls
+ .assume adl=1
+
+__bmuls:
+ push bc
+ ld c,a
+ mlt bc
+ ld a,c
+ pop bc
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/bmulu.src b/frontends/calculator/CEdev/lib/shared/bmulu.src index 20c27b5..a8413df 100644 --- a/frontends/calculator/CEdev/lib/shared/bmulu.src +++ b/frontends/calculator/CEdev/lib/shared/bmulu.src @@ -1,24 +1,24 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Unsigned Byte Multiply -; Input: -; Operand1: -; B : 8 bit -; -; Operand2: -; C : 8 bit -; -; Output: -; Result: A : 8 bit product -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __bmulu - .assume adl=1 - -__bmulu: - push bc - mlt bc - ld a,c - pop bc - ret +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Unsigned Byte Multiply
+; Input:
+; Operand1:
+; B : 8 bit
+;
+; Operand2:
+; C : 8 bit
+;
+; Output:
+; Result: A : 8 bit product
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __bmulu
+ .assume adl=1
+
+__bmulu:
+ push bc
+ mlt bc
+ ld a,c
+ pop bc
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/brems.src b/frontends/calculator/CEdev/lib/shared/brems.src index 3687ced..5a05f82 100644 --- a/frontends/calculator/CEdev/lib/shared/brems.src +++ b/frontends/calculator/CEdev/lib/shared/brems.src @@ -1,40 +1,40 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Signed Byte Modulus -; Input: -; Operand1: -; A : 8 bit dividend (numerator) -; -; Operand2: -; C : 8 bit divisor (denominator) -; -; Output: -; Result: A : 8 bit modulus -; Registers Used: -; -;------------------------------------------------------------------------- - .ref __bremu - .def __brems - .assume adl=1 - -__brems: - push bc - ld b,a - bit 7,c - jr z,skip1 - ld a,c - neg - ld c,a -skip1: - ld a,b - bit 7,a - jr z,skip2 - neg -skip2: - call __bremu - bit 7,b - jr z,skip3 - neg -skip3: - pop bc - ret +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Signed Byte Modulus
+; Input:
+; Operand1:
+; A : 8 bit dividend (numerator)
+;
+; Operand2:
+; C : 8 bit divisor (denominator)
+;
+; Output:
+; Result: A : 8 bit modulus
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .ref __bremu
+ .def __brems
+ .assume adl=1
+
+__brems:
+ push bc
+ ld b,a
+ bit 7,c
+ jr z,skip1
+ ld a,c
+ neg
+ ld c,a
+skip1:
+ ld a,b
+ bit 7,a
+ jr z,skip2
+ neg
+skip2:
+ call __bremu
+ bit 7,b
+ jr z,skip3
+ neg
+skip3:
+ pop bc
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/bremu.src b/frontends/calculator/CEdev/lib/shared/bremu.src index 4c60bc8..758e765 100644 --- a/frontends/calculator/CEdev/lib/shared/bremu.src +++ b/frontends/calculator/CEdev/lib/shared/bremu.src @@ -1,39 +1,39 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Unsigned Byte Modulus -; Input: -; Operand1: -; A : 8 bit dividend (numerator) -; -; Operand2: -; C : 8 bit divisor (denominator) -; -; Output: -; Result: A : 8 bit modulus -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __bremu - .assume adl=1 - -__bremu: - push bc - push hl - ld h,a - xor a,a - ld b,8 -loop: - sla h - rla - jr c,over - cp a,c - jr c,under -over: - sub a,c - inc h -under: - djnz loop - pop hl - pop bc - ret - +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Unsigned Byte Modulus
+; Input:
+; Operand1:
+; A : 8 bit dividend (numerator)
+;
+; Operand2:
+; C : 8 bit divisor (denominator)
+;
+; Output:
+; Result: A : 8 bit modulus
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __bremu
+ .assume adl=1
+
+__bremu:
+ push bc
+ push hl
+ ld h,a
+ xor a,a
+ ld b,8
+loop:
+ sla h
+ rla
+ jr c,over
+ cp a,c
+ jr c,under
+over:
+ sub a,c
+ inc h
+under:
+ djnz loop
+ pop hl
+ pop bc
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/bshl.src b/frontends/calculator/CEdev/lib/shared/bshl.src index 9c6c14b..2688b9e 100644 --- a/frontends/calculator/CEdev/lib/shared/bshl.src +++ b/frontends/calculator/CEdev/lib/shared/bshl.src @@ -1,18 +1,18 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Byte Shift Left -; Input: -; Operand1: -; A : 8 bit number to shift -; Operand2: -; B : 8 bit shift count -; -; Output: -; Result: A : 8 bit -; Registers Used: -; flags -;------------------------------------------------------------------------- - .def __bshl - .assume adl=1 - -__bshl equ 000100h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Byte Shift Left
+; Input:
+; Operand1:
+; A : 8 bit number to shift
+; Operand2:
+; B : 8 bit shift count
+;
+; Output:
+; Result: A : 8 bit
+; Registers Used:
+; flags
+;-------------------------------------------------------------------------
+ .def __bshl
+ .assume adl=1
+
+__bshl equ 000100h
diff --git a/frontends/calculator/CEdev/lib/shared/bshrs.src b/frontends/calculator/CEdev/lib/shared/bshrs.src index 4c53262..7a3fd54 100644 --- a/frontends/calculator/CEdev/lib/shared/bshrs.src +++ b/frontends/calculator/CEdev/lib/shared/bshrs.src @@ -1,29 +1,29 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Byte Shift Right Signed -; Input: -; Operand1: -; A : 8 bit number to shift -; Operand2: -; B : 8 bit shift count -; -; Output: -; Result: A : 8 bit -; Registers Used: -; flags -;------------------------------------------------------------------------- - .def __bshrs - .assume adl=1 - -__bshrs: - push bc - inc b - jr test - -loop: - sra a -test: - djnz loop - - pop bc - ret +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Byte Shift Right Signed
+; Input:
+; Operand1:
+; A : 8 bit number to shift
+; Operand2:
+; B : 8 bit shift count
+;
+; Output:
+; Result: A : 8 bit
+; Registers Used:
+; flags
+;-------------------------------------------------------------------------
+ .def __bshrs
+ .assume adl=1
+
+__bshrs:
+ push bc
+ inc b
+ jr test
+
+loop:
+ sra a
+test:
+ djnz loop
+
+ pop bc
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/bshru.src b/frontends/calculator/CEdev/lib/shared/bshru.src index ec73588..8b13d56 100644 --- a/frontends/calculator/CEdev/lib/shared/bshru.src +++ b/frontends/calculator/CEdev/lib/shared/bshru.src @@ -1,18 +1,18 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Byte Shift Right Unsigned -; Input: -; Operand1: -; A : 8 bit number to shift -; Operand2: -; B : 8 bit shift count -; -; Output: -; Result: A : 8 bit -; Registers Used: -; flags -;------------------------------------------------------------------------- - .def __bshru - .assume adl=1 - -__bshru equ 000104h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Byte Shift Right Unsigned
+; Input:
+; Operand1:
+; A : 8 bit number to shift
+; Operand2:
+; B : 8 bit shift count
+;
+; Output:
+; Result: A : 8 bit
+; Registers Used:
+; flags
+;-------------------------------------------------------------------------
+ .def __bshru
+ .assume adl=1
+
+__bshru equ 000104h
diff --git a/frontends/calculator/CEdev/lib/shared/bstix.src b/frontends/calculator/CEdev/lib/shared/bstix.src index 3719b30..1fec2dd 100644 --- a/frontends/calculator/CEdev/lib/shared/bstix.src +++ b/frontends/calculator/CEdev/lib/shared/bstix.src @@ -1,19 +1,19 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; byte store (ix+nnnnnn),A -; Input: -; Operand1: -; BC : 24-bit offset from ix -; A : 8-bit integer to store -; -; Output: -; none -; -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __bstix - .assume adl=1 - -__bstix equ 00010Ch - +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; byte store (ix+nnnnnn),A
+; Input:
+; Operand1:
+; BC : 24-bit offset from ix
+; A : 8-bit integer to store
+;
+; Output:
+; none
+;
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __bstix
+ .assume adl=1
+
+__bstix equ 00010Ch
+
diff --git a/frontends/calculator/CEdev/lib/shared/bstiy.src b/frontends/calculator/CEdev/lib/shared/bstiy.src index b95ce91..98a9d00 100644 --- a/frontends/calculator/CEdev/lib/shared/bstiy.src +++ b/frontends/calculator/CEdev/lib/shared/bstiy.src @@ -1,18 +1,18 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; byte store (iy+nnnnnn),A -; Input: -; Operand1: -; BC : 24-bit offset from iy -; A : 8-bit integer to store -; -; Output: -; -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __bstiy - .assume adl=1 - -__bstiy equ 000108h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; byte store (iy+nnnnnn),A
+; Input:
+; Operand1:
+; BC : 24-bit offset from iy
+; A : 8-bit integer to store
+;
+; Output:
+;
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __bstiy
+ .assume adl=1
+
+__bstiy equ 000108h
diff --git a/frontends/calculator/CEdev/lib/shared/calloc.src b/frontends/calculator/CEdev/lib/shared/calloc.src index 069e4bf..73d5704 100644 --- a/frontends/calculator/CEdev/lib/shared/calloc.src +++ b/frontends/calculator/CEdev/lib/shared/calloc.src @@ -1,27 +1,27 @@ - .ref __imulu - .ref _malloc - .ref _memset - .def _calloc - .assume adl=1 - -_calloc: - pop de - pop bc - pop hl - push hl - push bc - push de - call __imulu - push hl - call _malloc - add hl,de - xor a,a - sbc hl,de - ld e,a - push de - push hl - call nz,_memset - pop hl - pop de - pop bc - ret + .ref __imulu
+ .ref _malloc
+ .ref _memset
+ .def _calloc
+ .assume adl=1
+
+_calloc:
+ pop de
+ pop bc
+ pop hl
+ push hl
+ push bc
+ push de
+ call __imulu
+ push hl
+ call _malloc
+ add hl,de
+ xor a,a
+ sbc hl,de
+ ld e,a
+ push de
+ push hl
+ call nz,_memset
+ pop hl
+ pop de
+ pop bc
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/case.src b/frontends/calculator/CEdev/lib/shared/case.src index 26919eb..c2fc6c4 100644 --- a/frontends/calculator/CEdev/lib/shared/case.src +++ b/frontends/calculator/CEdev/lib/shared/case.src @@ -1,27 +1,27 @@ -; (c) Copyright 2001-2008 Zilog Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand1: -; bc : 24 bit address of CASE TABLE -; -; Operand2: -; de : 24 bit number of entries in table -; -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; Result: hl : 24 bit address of case jp to take -; Registers Used: -; -; -; Table Format: -; [24-bit value][JP label (4-bytes)] 7 bytes total -; -;------------------------------------------------------------------------- - .def __case - .assume adl=1 - -__case equ 000110h +; (c) Copyright 2001-2008 Zilog Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand1:
+; bc : 24 bit address of CASE TABLE
+;
+; Operand2:
+; de : 24 bit number of entries in table
+;
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+; Result: hl : 24 bit address of case jp to take
+; Registers Used:
+;
+;
+; Table Format:
+; [24-bit value][JP label (4-bytes)] 7 bytes total
+;
+;-------------------------------------------------------------------------
+ .def __case
+ .assume adl=1
+
+__case equ 000110h
diff --git a/frontends/calculator/CEdev/lib/shared/case16.src b/frontends/calculator/CEdev/lib/shared/case16.src index 33cb5cc..4d25c76 100644 --- a/frontends/calculator/CEdev/lib/shared/case16.src +++ b/frontends/calculator/CEdev/lib/shared/case16.src @@ -1,17 +1,17 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __case16 - .assume adl=1 - -__case16 equ 000114h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __case16
+ .assume adl=1
+
+__case16 equ 000114h
diff --git a/frontends/calculator/CEdev/lib/shared/case16d.src b/frontends/calculator/CEdev/lib/shared/case16d.src index f2a929d..21f47d9 100644 --- a/frontends/calculator/CEdev/lib/shared/case16d.src +++ b/frontends/calculator/CEdev/lib/shared/case16d.src @@ -1,17 +1,17 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; Result: hl : 24 bit address of case jp to take -; Registers Used: -; -;------------------------------------------------------------------------- - .def __case16D - .assume adl=1 - -__case16D equ 000118h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+; Result: hl : 24 bit address of case jp to take
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __case16D
+ .assume adl=1
+
+__case16D equ 000118h
diff --git a/frontends/calculator/CEdev/lib/shared/case24.src b/frontends/calculator/CEdev/lib/shared/case24.src index 43539e5..de39859 100644 --- a/frontends/calculator/CEdev/lib/shared/case24.src +++ b/frontends/calculator/CEdev/lib/shared/case24.src @@ -1,17 +1,17 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __case24 - .assume adl=1 - -__case24 equ 00011Ch +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __case24
+ .assume adl=1
+
+__case24 equ 00011Ch
diff --git a/frontends/calculator/CEdev/lib/shared/case24d.src b/frontends/calculator/CEdev/lib/shared/case24d.src index bdec1ac..8ebfbc0 100644 --- a/frontends/calculator/CEdev/lib/shared/case24d.src +++ b/frontends/calculator/CEdev/lib/shared/case24d.src @@ -1,17 +1,17 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; Result: hl : 24 bit address of case jp to take -; Registers Used: -; -;------------------------------------------------------------------------- - .def __case24D - .assume adl=1 - -__case24D equ 000120h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+; Result: hl : 24 bit address of case jp to take
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __case24D
+ .assume adl=1
+
+__case24D equ 000120h
diff --git a/frontends/calculator/CEdev/lib/shared/case8.src b/frontends/calculator/CEdev/lib/shared/case8.src index 8d4f00f..da200d6 100644 --- a/frontends/calculator/CEdev/lib/shared/case8.src +++ b/frontends/calculator/CEdev/lib/shared/case8.src @@ -1,17 +1,17 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __case8 - .assume adl=1 - -__case8 equ 000124h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __case8
+ .assume adl=1
+
+__case8 equ 000124h
diff --git a/frontends/calculator/CEdev/lib/shared/case8d.src b/frontends/calculator/CEdev/lib/shared/case8d.src index f4be7a6..52ade6f 100644 --- a/frontends/calculator/CEdev/lib/shared/case8d.src +++ b/frontends/calculator/CEdev/lib/shared/case8d.src @@ -1,17 +1,17 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; Result: hl : 24 bit address of case jp to take -; Registers Used: -; -;------------------------------------------------------------------------- - .def __case8D - .assume adl=1 - -__case8D equ 000128h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+; Result: hl : 24 bit address of case jp to take
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __case8D
+ .assume adl=1
+
+__case8D equ 000128h
diff --git a/frontends/calculator/CEdev/lib/shared/debugger.src b/frontends/calculator/CEdev/lib/shared/debugger.src index 684b3a2..bc6a4a4 100644 --- a/frontends/calculator/CEdev/lib/shared/debugger.src +++ b/frontends/calculator/CEdev/lib/shared/debugger.src @@ -1,12 +1,12 @@ -; --- -; opens the debugger -; --- - - .def _dbg_Debugger - .assume adl=1 - -_dbg_Debugger: - scf - sbc hl,hl - ld (hl),2 - ret +; ---
+; opens the debugger
+; ---
+
+ .def _dbg_Debugger
+ .assume adl=1
+
+_dbg_Debugger:
+ scf
+ sbc hl,hl
+ ld (hl),2
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/delay.src b/frontends/calculator/CEdev/lib/shared/delay.src index 62978b8..affa948 100644 --- a/frontends/calculator/CEdev/lib/shared/delay.src +++ b/frontends/calculator/CEdev/lib/shared/delay.src @@ -1,92 +1,92 @@ - -; --- -; void delay(uint16_t millis) -; --- - - .def _delay - .assume adl=1 - -mpTmrRange equ 0F20000h - -tmr2Counter equ 10h -tmr2Load equ 14h -tmr2Match1 equ 18h -tmr2Match2 equ 1Ch - -tmrCtrl equ 30h - -bTmr2Enable equ 3 -bTmr2Crystal equ 4 -bTmr2Overflow equ 5 -bTmr2CountUp equ 10 - -_delay: -; Read argument. - pop de - ex (sp),hl ; 0hl = millis - push de -; Abort ASAP if millis == 0. - ld a,h - or a,l - ret z -; Convert millis to CPU cycles by multiplying by 48000. -; Subtract 2 to offset overhead and the unknown counter low byte. - ld b,h - ld c,l ; 0bc = millis - dec.s bc ; bc = millis-1; need to set bcu = 0 - srl b - rr c ; bc = (millis-1)>>1 - ; = millis*(48000&0FFh)>>8, - ; off by -1 or -0.5 - ld e,l - ld d,187 ; 48000/256 == 187.5 - ld l,d - mlt de ; de = (millis&0FFh)*(48000>>8) - mlt hl ; hl = (millis>>8)*(48000>>8) - dec hl - push hl - dec sp - pop hl - inc sp - ld l,-2 ; hl = (millis&0FF00h)*(48000>>8)-2 - add hl,de ; hl = millis*(48000>>8)-2 - add hl,bc ; hl ~ (millis*48000>>8)-3 -; Set up timer 2 control bits: disabled, CPU clock, no interrupt, count down. - ex de,hl ; de ~ (millis*48000>>8)-3 - ld hl,mpTmrRange+tmrCtrl - res bTmr2Enable,(hl) - res bTmr2Crystal,(hl) - res bTmr2Overflow,(hl) - inc hl - res bTmr2CountUp-8,(hl) -; Set up timer 2 counter, match, and reload values. - ld l,tmr2Counter+1 - ld (hl),de ; counter = millis*48000-768+0xxh - ld l,tmr2Match1+3 - ld (hl),0FFh ; match1 = 0FFxxxxxxh - ld l,tmr2Match2+3 - ld (hl),0FFh ; match2 = 0FFxxxxxxh - ld l,tmr2Load+3 - ld (hl),0FEh ; reload = 0FExxxxxxh -; Enable timer 2. - ld l,tmrCtrl - set bTmr2Enable,(hl) -; Wait until timer 2 expires (underflows). -; Will catch the underflow if not interrupted for a continuous period of -; ((254-188)<<24)/48000000 ~ 23.1s. - ld l,tmr2Counter+3 - ld a,188 ; = 1+((0FFFFh*24000 shl 1)-12 shr 24) -; 380 cc up to this point -_delay_wait: - cp a,(hl) - jr nc,_delay_wait -; 12-29 cc to exit waitloop -; Done. - ret -; ~421 cc up to this point -; caller overhead: -; ld bc,millis -; push bc -; call _delay -; pop bc -; ~485 cc total +
+; ---
+; void delay(uint16_t millis)
+; ---
+
+ .def _delay
+ .assume adl=1
+
+mpTmrRange equ 0F20000h
+
+tmr2Counter equ 10h
+tmr2Load equ 14h
+tmr2Match1 equ 18h
+tmr2Match2 equ 1Ch
+
+tmrCtrl equ 30h
+
+bTmr2Enable equ 3
+bTmr2Crystal equ 4
+bTmr2Overflow equ 5
+bTmr2CountUp equ 10
+
+_delay:
+; Read argument.
+ pop de
+ ex (sp),hl ; 0hl = millis
+ push de
+; Abort ASAP if millis == 0.
+ ld a,h
+ or a,l
+ ret z
+; Convert millis to CPU cycles by multiplying by 48000.
+; Subtract 2 to offset overhead and the unknown counter low byte.
+ ld b,h
+ ld c,l ; 0bc = millis
+ dec.s bc ; bc = millis-1; need to set bcu = 0
+ srl b
+ rr c ; bc = (millis-1)>>1
+ ; = millis*(48000&0FFh)>>8,
+ ; off by -1 or -0.5
+ ld e,l
+ ld d,187 ; 48000/256 == 187.5
+ ld l,d
+ mlt de ; de = (millis&0FFh)*(48000>>8)
+ mlt hl ; hl = (millis>>8)*(48000>>8)
+ dec hl
+ push hl
+ dec sp
+ pop hl
+ inc sp
+ ld l,-2 ; hl = (millis&0FF00h)*(48000>>8)-2
+ add hl,de ; hl = millis*(48000>>8)-2
+ add hl,bc ; hl ~ (millis*48000>>8)-3
+; Set up timer 2 control bits: disabled, CPU clock, no interrupt, count down.
+ ex de,hl ; de ~ (millis*48000>>8)-3
+ ld hl,mpTmrRange+tmrCtrl
+ res bTmr2Enable,(hl)
+ res bTmr2Crystal,(hl)
+ res bTmr2Overflow,(hl)
+ inc hl
+ res bTmr2CountUp-8,(hl)
+; Set up timer 2 counter, match, and reload values.
+ ld l,tmr2Counter+1
+ ld (hl),de ; counter = millis*48000-768+0xxh
+ ld l,tmr2Match1+3
+ ld (hl),0FFh ; match1 = 0FFxxxxxxh
+ ld l,tmr2Match2+3
+ ld (hl),0FFh ; match2 = 0FFxxxxxxh
+ ld l,tmr2Load+3
+ ld (hl),0FEh ; reload = 0FExxxxxxh
+; Enable timer 2.
+ ld l,tmrCtrl
+ set bTmr2Enable,(hl)
+; Wait until timer 2 expires (underflows).
+; Will catch the underflow if not interrupted for a continuous period of
+; ((254-188)<<24)/48000000 ~ 23.1s.
+ ld l,tmr2Counter+3
+ ld a,188 ; = 1+((0FFFFh*24000 shl 1)-12 shr 24)
+; 380 cc up to this point
+_delay_wait:
+ cp a,(hl)
+ jr nc,_delay_wait
+; 12-29 cc to exit waitloop
+; Done.
+ ret
+; ~421 cc up to this point
+; caller overhead:
+; ld bc,millis
+; push bc
+; call _delay
+; pop bc
+; ~485 cc total
diff --git a/frontends/calculator/CEdev/lib/shared/div.src b/frontends/calculator/CEdev/lib/shared/div.src index 0ae3c0d..030a767 100644 --- a/frontends/calculator/CEdev/lib/shared/div.src +++ b/frontends/calculator/CEdev/lib/shared/div.src @@ -1,54 +1,54 @@ -; Copyright 1992-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Div function -; -; div_t div(int numer,int denom); -; -;------------------------------------------------------------------------- - .def _div - .ref __idivs - .ref __irems - .assume adl=1 - -_div: - push af - push bc - push hl - push de - - ld hl,21 - add hl,sp - ld bc,(hl) ; bc=val of denominator - dec hl - dec hl - dec hl - ld hl,(hl) ; hl=val of numerator - push hl - call __idivs - ex de,hl ; de= quotient - pop hl ; hl=val of numerator - call __irems - ld bc,hl - - ld hl,15 - add hl,sp - ld hl,(hl) - inc hl - inc hl - inc hl - ld (hl),bc ; remainder - dec hl - dec hl - dec hl - ld (hl),de ;quotient - - pop de - pop bc - pop bc - pop af - - ret - - - - +; Copyright 1992-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Div function
+;
+; div_t div(int numer,int denom);
+;
+;-------------------------------------------------------------------------
+ .def _div
+ .ref __idivs
+ .ref __irems
+ .assume adl=1
+
+_div:
+ push af
+ push bc
+ push hl
+ push de
+
+ ld hl,21
+ add hl,sp
+ ld bc,(hl) ; bc=val of denominator
+ dec hl
+ dec hl
+ dec hl
+ ld hl,(hl) ; hl=val of numerator
+ push hl
+ call __idivs
+ ex de,hl ; de= quotient
+ pop hl ; hl=val of numerator
+ call __irems
+ ld bc,hl
+
+ ld hl,15
+ add hl,sp
+ ld hl,(hl)
+ inc hl
+ inc hl
+ inc hl
+ ld (hl),bc ; remainder
+ dec hl
+ dec hl
+ dec hl
+ ld (hl),de ;quotient
+
+ pop de
+ pop bc
+ pop bc
+ pop af
+
+ ret
+
+
+
+
diff --git a/frontends/calculator/CEdev/lib/shared/dzx7_standard.src b/frontends/calculator/CEdev/lib/shared/dzx7_standard.src index a3591a2..9b71b89 100644 --- a/frontends/calculator/CEdev/lib/shared/dzx7_standard.src +++ b/frontends/calculator/CEdev/lib/shared/dzx7_standard.src @@ -1,106 +1,106 @@ -; --- -; void dzx7_turbo(void *src, void *dst) -; --- -; Dec 2012 by Einar Saukas & Urusergi -; "Standard" version (70 bytes) -; --- - - .def _dzx7_Standard - .assume adl=1 - -; enter : hl = void *src -; de = void *dst -; -; exit : hl = & following uncompressed block -; -; uses : af, bc, de, hl - -_dzx7_Standard: - pop bc - pop hl - pop de - push de - push hl - push bc - - ld a, 128 - -dzx7s_copy_byte_loop: - - ldi ; copy literal byte - -dzx7s_main_loop: - - call dzx7s_next_bit - jr nc, dzx7s_copy_byte_loop ; next bit indicates either literal or sequence - -; determine number of bits used for length (Elias gamma coding) - - push de - ld de, 0 - ld bc, 0 - -dzx7s_len_size_loop: - - inc d - call dzx7s_next_bit - jr nc, dzx7s_len_size_loop - -; determine length - -dzx7s_len_value_loop: - - call nc, dzx7s_next_bit - rl c - rl b - jr c, dzx7s_exit ; check end marker - dec d - jr nz, dzx7s_len_value_loop - inc bc ; adjust length - -; determine offset - - ld e, (hl) ; load offset flag (1 bit) + offset value (7 bits) - inc hl - - sla e - inc e - - jr nc, dzx7s_offset_end ; if offset flag is set, load 4 extra bits - ld d, 16 ; bit marker to load 4 bits - -dzx7s_rld_next_bit: - - call dzx7s_next_bit - rl d ; insert next bit into D - jr nc, dzx7s_rld_next_bit ; repeat 4 times, until bit marker is out - inc d ; add 128 to DE - srl d ; retrieve fourth bit from D - -dzx7s_offset_end: - - rr e ; insert fourth bit into E - -; copy previous sequence - - ex (sp), hl ; store source, restore destination - push hl ; store destination - sbc hl, de ; HL = destination - offset - 1 - pop de ; DE = destination - ldir - -dzx7s_exit: - - pop hl ; restore source address (compressed data) - jr nc, dzx7s_main_loop - -dzx7s_next_bit: - - add a, a ; check next bit - ret nz ; no more bits left? - ld a, (hl) ; load another group of 8 bits - inc hl - rla - ret - - end +; ---
+; void dzx7_turbo(void *src, void *dst)
+; ---
+; Dec 2012 by Einar Saukas & Urusergi
+; "Standard" version (70 bytes)
+; ---
+
+ .def _dzx7_Standard
+ .assume adl=1
+
+; enter : hl = void *src
+; de = void *dst
+;
+; exit : hl = & following uncompressed block
+;
+; uses : af, bc, de, hl
+
+_dzx7_Standard:
+ pop bc
+ pop hl
+ pop de
+ push de
+ push hl
+ push bc
+
+ ld a, 128
+
+dzx7s_copy_byte_loop:
+
+ ldi ; copy literal byte
+
+dzx7s_main_loop:
+
+ call dzx7s_next_bit
+ jr nc, dzx7s_copy_byte_loop ; next bit indicates either literal or sequence
+
+; determine number of bits used for length (Elias gamma coding)
+
+ push de
+ ld de, 0
+ ld bc, 0
+
+dzx7s_len_size_loop:
+
+ inc d
+ call dzx7s_next_bit
+ jr nc, dzx7s_len_size_loop
+
+; determine length
+
+dzx7s_len_value_loop:
+
+ call nc, dzx7s_next_bit
+ rl c
+ rl b
+ jr c, dzx7s_exit ; check end marker
+ dec d
+ jr nz, dzx7s_len_value_loop
+ inc bc ; adjust length
+
+; determine offset
+
+ ld e, (hl) ; load offset flag (1 bit) + offset value (7 bits)
+ inc hl
+
+ sla e
+ inc e
+
+ jr nc, dzx7s_offset_end ; if offset flag is set, load 4 extra bits
+ ld d, 16 ; bit marker to load 4 bits
+
+dzx7s_rld_next_bit:
+
+ call dzx7s_next_bit
+ rl d ; insert next bit into D
+ jr nc, dzx7s_rld_next_bit ; repeat 4 times, until bit marker is out
+ inc d ; add 128 to DE
+ srl d ; retrieve fourth bit from D
+
+dzx7s_offset_end:
+
+ rr e ; insert fourth bit into E
+
+; copy previous sequence
+
+ ex (sp), hl ; store source, restore destination
+ push hl ; store destination
+ sbc hl, de ; HL = destination - offset - 1
+ pop de ; DE = destination
+ ldir
+
+dzx7s_exit:
+
+ pop hl ; restore source address (compressed data)
+ jr nc, dzx7s_main_loop
+
+dzx7s_next_bit:
+
+ add a, a ; check next bit
+ ret nz ; no more bits left?
+ ld a, (hl) ; load another group of 8 bits
+ inc hl
+ rla
+ ret
+
+ end
diff --git a/frontends/calculator/CEdev/lib/shared/dzx7_turbo.src b/frontends/calculator/CEdev/lib/shared/dzx7_turbo.src index 15a6236..cd54eae 100644 --- a/frontends/calculator/CEdev/lib/shared/dzx7_turbo.src +++ b/frontends/calculator/CEdev/lib/shared/dzx7_turbo.src @@ -1,117 +1,117 @@ -; --- -; void dzx7_turbo(void *src, void *dst) -; --- -; Dec 2012 by Einar Saukas & Urusergi -; "Turbo" version (89 bytes, 25% faster) -; --- - - .def _dzx7_Turbo - .assume adl=1 - -; enter : hl = void *src -; de = void *dst -; -; exit : hl = & following uncompressed block -; -; uses : af, bc, de, hl - -_dzx7_Turbo: - pop bc - pop hl - pop de - push de - push hl - push bc - - ld a, 128 - -dzx7t_copy_byte_loop: - - ldi ; copy literal byte - -dzx7t_main_loop: - - add a, a ; check next bit - call z, dzx7t_load_bits ; no more bits left? - jr nc, dzx7t_copy_byte_loop ; next bit indicates either literal or sequence - -; determine number of bits used for length (Elias gamma coding) - - push de - ld de, 0 - ld bc, 1 - -dzx7t_len_size_loop: - - inc d - add a, a ; check next bit - call z, dzx7t_load_bits ; no more bits left? - jr nc, dzx7t_len_size_loop - jp dzx7t_len_value_start - -; determine length - -dzx7t_len_value_loop: - - add a, a ; check next bit - call z, dzx7t_load_bits ; no more bits left? - rl c - rl b - jr c, dzx7t_exit ; check end marker - -dzx7t_len_value_start: - - dec d - jr nz, dzx7t_len_value_loop - inc bc ; adjust length - -; determine offset - - ld e, (hl) ; load offset flag (1 bit) + offset value (7 bits) - inc hl - - sla e - inc e - - jr nc, dzx7t_offset_end ; if offset flag is set, load 4 extra bits - add a, a ; check next bit - call z, dzx7t_load_bits ; no more bits left? - rl d ; insert first bit into D - add a, a ; check next bit - call z, dzx7t_load_bits ; no more bits left? - rl d ; insert second bit into D - add a, a ; check next bit - call z, dzx7t_load_bits ; no more bits left? - rl d ; insert third bit into D - add a, a ; check next bit - call z, dzx7t_load_bits ; no more bits left? - ccf - jr c, dzx7t_offset_end - inc d ; equivalent to adding 128 to DE - -dzx7t_offset_end: - - rr e ; insert inverted fourth bit into E - -; copy previous sequence - - ex (sp), hl ; store source, restore destination - push hl ; store destination - sbc hl, de ; HL = destination - offset - 1 - pop de ; DE = destination - ldir - -dzx7t_exit: - - pop hl ; restore source address (compressed data) - jp nc, dzx7t_main_loop - -dzx7t_load_bits: - - ld a, (hl) ; load another group of 8 bits - inc hl - rla - ret - - - end +; ---
+; void dzx7_turbo(void *src, void *dst)
+; ---
+; Dec 2012 by Einar Saukas & Urusergi
+; "Turbo" version (89 bytes, 25% faster)
+; ---
+
+ .def _dzx7_Turbo
+ .assume adl=1
+
+; enter : hl = void *src
+; de = void *dst
+;
+; exit : hl = & following uncompressed block
+;
+; uses : af, bc, de, hl
+
+_dzx7_Turbo:
+ pop bc
+ pop hl
+ pop de
+ push de
+ push hl
+ push bc
+
+ ld a, 128
+
+dzx7t_copy_byte_loop:
+
+ ldi ; copy literal byte
+
+dzx7t_main_loop:
+
+ add a, a ; check next bit
+ call z, dzx7t_load_bits ; no more bits left?
+ jr nc, dzx7t_copy_byte_loop ; next bit indicates either literal or sequence
+
+; determine number of bits used for length (Elias gamma coding)
+
+ push de
+ ld de, 0
+ ld bc, 1
+
+dzx7t_len_size_loop:
+
+ inc d
+ add a, a ; check next bit
+ call z, dzx7t_load_bits ; no more bits left?
+ jr nc, dzx7t_len_size_loop
+ jp dzx7t_len_value_start
+
+; determine length
+
+dzx7t_len_value_loop:
+
+ add a, a ; check next bit
+ call z, dzx7t_load_bits ; no more bits left?
+ rl c
+ rl b
+ jr c, dzx7t_exit ; check end marker
+
+dzx7t_len_value_start:
+
+ dec d
+ jr nz, dzx7t_len_value_loop
+ inc bc ; adjust length
+
+; determine offset
+
+ ld e, (hl) ; load offset flag (1 bit) + offset value (7 bits)
+ inc hl
+
+ sla e
+ inc e
+
+ jr nc, dzx7t_offset_end ; if offset flag is set, load 4 extra bits
+ add a, a ; check next bit
+ call z, dzx7t_load_bits ; no more bits left?
+ rl d ; insert first bit into D
+ add a, a ; check next bit
+ call z, dzx7t_load_bits ; no more bits left?
+ rl d ; insert second bit into D
+ add a, a ; check next bit
+ call z, dzx7t_load_bits ; no more bits left?
+ rl d ; insert third bit into D
+ add a, a ; check next bit
+ call z, dzx7t_load_bits ; no more bits left?
+ ccf
+ jr c, dzx7t_offset_end
+ inc d ; equivalent to adding 128 to DE
+
+dzx7t_offset_end:
+
+ rr e ; insert inverted fourth bit into E
+
+; copy previous sequence
+
+ ex (sp), hl ; store source, restore destination
+ push hl ; store destination
+ sbc hl, de ; HL = destination - offset - 1
+ pop de ; DE = destination
+ ldir
+
+dzx7t_exit:
+
+ pop hl ; restore source address (compressed data)
+ jp nc, dzx7t_main_loop
+
+dzx7t_load_bits:
+
+ ld a, (hl) ; load another group of 8 bits
+ inc hl
+ rla
+ ret
+
+
+ end
diff --git a/frontends/calculator/CEdev/lib/shared/finite.src b/frontends/calculator/CEdev/lib/shared/finite.src index 35c8c5c..2b55337 100644 --- a/frontends/calculator/CEdev/lib/shared/finite.src +++ b/frontends/calculator/CEdev/lib/shared/finite.src @@ -1,19 +1,19 @@ - .def _finite - .assume adl=1 - -; int finite(double n); - -_finite: - pop bc - pop hl - pop de - push de - push hl - push bc - add hl,hl - ld a,e - rla - add a,1 - sbc hl,hl - inc hl - ret + .def _finite
+ .assume adl=1
+
+; int finite(double n);
+
+_finite:
+ pop bc
+ pop hl
+ pop de
+ push de
+ push hl
+ push bc
+ add hl,hl
+ ld a,e
+ rla
+ add a,1
+ sbc hl,hl
+ inc hl
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/fpadd.src b/frontends/calculator/CEdev/lib/shared/fpadd.src index 238ee39..696867b 100644 --- a/frontends/calculator/CEdev/lib/shared/fpadd.src +++ b/frontends/calculator/CEdev/lib/shared/fpadd.src @@ -1,25 +1,25 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; IEEE Single precision add -; -; INPUTS: AuBC OP1. -; EuHL OP2. -; -; OUTPUTS: AuBC Sum. -; -; Returns the result of adding the absolute values of the single-precision -; floating-point values OP1 and OP2. If Sign of result is 1, the sum is -; negated before being returned. -; -;-------------------------------------------------------------- - .def __fadd - .assume adl=1 - -__fadd equ 000270h +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; IEEE Single precision add
+;
+; INPUTS: AuBC OP1.
+; EuHL OP2.
+;
+; OUTPUTS: AuBC Sum.
+;
+; Returns the result of adding the absolute values of the single-precision
+; floating-point values OP1 and OP2. If Sign of result is 1, the sum is
+; negated before being returned.
+;
+;--------------------------------------------------------------
+ .def __fadd
+ .assume adl=1
+
+__fadd equ 000270h
diff --git a/frontends/calculator/CEdev/lib/shared/fpcmp.src b/frontends/calculator/CEdev/lib/shared/fpcmp.src index acfbce0..1e1df2e 100644 --- a/frontends/calculator/CEdev/lib/shared/fpcmp.src +++ b/frontends/calculator/CEdev/lib/shared/fpcmp.src @@ -1,27 +1,27 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; IEEE Single precision compare. -; -; INPUTS: -; -; Operand1: -; EuHL : 32 bit IEEE format -; -; Operand2: -; AuBC : 32 bit IEEE format -; -; -; OUTPUTS: FLAGS based on Op1 - Op2 -; -;-------------------------------------------------------------- - .def __fcmp - .assume adl=1 - -__fcmp equ 000274h +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; IEEE Single precision compare.
+;
+; INPUTS:
+;
+; Operand1:
+; EuHL : 32 bit IEEE format
+;
+; Operand2:
+; AuBC : 32 bit IEEE format
+;
+;
+; OUTPUTS: FLAGS based on Op1 - Op2
+;
+;--------------------------------------------------------------
+ .def __fcmp
+ .assume adl=1
+
+__fcmp equ 000274h
diff --git a/frontends/calculator/CEdev/lib/shared/fpdiv.src b/frontends/calculator/CEdev/lib/shared/fpdiv.src index ab80d15..f8ec9e1 100644 --- a/frontends/calculator/CEdev/lib/shared/fpdiv.src +++ b/frontends/calculator/CEdev/lib/shared/fpdiv.src @@ -1,28 +1,28 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; IEEE Single precision division -; -; INPUTS: -; Operand1: -; AuBC : 32 bit IEEE format -; -; Operand2: -; EuHL : 32 bit IEEE format divisor -; -; OUTPUTS: -; Result: AuBC : 32 bit IEEE Quotient. -; Registers Used: -; flags -; -;-------------------------------------------------------------- - .def __fdiv - .assume adl=1 - -__fdiv equ 000278h +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; IEEE Single precision division
+;
+; INPUTS:
+; Operand1:
+; AuBC : 32 bit IEEE format
+;
+; Operand2:
+; EuHL : 32 bit IEEE format divisor
+;
+; OUTPUTS:
+; Result: AuBC : 32 bit IEEE Quotient.
+; Registers Used:
+; flags
+;
+;--------------------------------------------------------------
+ .def __fdiv
+ .assume adl=1
+
+__fdiv equ 000278h
diff --git a/frontends/calculator/CEdev/lib/shared/fpftol.src b/frontends/calculator/CEdev/lib/shared/fpftol.src index bc4e01e..4e21a05 100644 --- a/frontends/calculator/CEdev/lib/shared/fpftol.src +++ b/frontends/calculator/CEdev/lib/shared/fpftol.src @@ -1,20 +1,20 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; IEEE Single precision to long. -; -; INPUTS: abc: 32-bit IEEE Single precision. -; -; OUTPUTS: abc: 32-bit signed long. -; -;-------------------------------------------------------------- - .def __ftol - .assume adl=1 - -__ftol equ 00027Ch +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; IEEE Single precision to long.
+;
+; INPUTS: abc: 32-bit IEEE Single precision.
+;
+; OUTPUTS: abc: 32-bit signed long.
+;
+;--------------------------------------------------------------
+ .def __ftol
+ .assume adl=1
+
+__ftol equ 00027Ch
diff --git a/frontends/calculator/CEdev/lib/shared/fpltof.src b/frontends/calculator/CEdev/lib/shared/fpltof.src index ba2e70f..19b4dbb 100644 --- a/frontends/calculator/CEdev/lib/shared/fpltof.src +++ b/frontends/calculator/CEdev/lib/shared/fpltof.src @@ -1,20 +1,20 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; Signed long to IEEE Single precision. -; -; INPUTS: AuBC 32-bit signed long. -; -; OUTPUTS: AuBC 32-bit IEEE Single precision. -; -;-------------------------------------------------------------- - .def __ltof - .assume adl=1 - -__ltof equ 000284h +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; Signed long to IEEE Single precision.
+;
+; INPUTS: AuBC 32-bit signed long.
+;
+; OUTPUTS: AuBC 32-bit IEEE Single precision.
+;
+;--------------------------------------------------------------
+ .def __ltof
+ .assume adl=1
+
+__ltof equ 000284h
diff --git a/frontends/calculator/CEdev/lib/shared/fpmul.src b/frontends/calculator/CEdev/lib/shared/fpmul.src index 7b59483..3080acd 100644 --- a/frontends/calculator/CEdev/lib/shared/fpmul.src +++ b/frontends/calculator/CEdev/lib/shared/fpmul.src @@ -1,26 +1,26 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;------------------------------------------------------------------------- -; IEEE Single precision multiply -; Input: -; Operand1: -; AuBC : 32 bit -; -; Operand2: -; EuHL : 32 bit -; -; Output: -; Result: AuBC : 32 bit -; Registers Used: -; flags -; -;------------------------------------------------------------------------- - .def __fmul - .assume adl=1 - -__fmul equ 000288h +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;-------------------------------------------------------------------------
+; IEEE Single precision multiply
+; Input:
+; Operand1:
+; AuBC : 32 bit
+;
+; Operand2:
+; EuHL : 32 bit
+;
+; Output:
+; Result: AuBC : 32 bit
+; Registers Used:
+; flags
+;
+;-------------------------------------------------------------------------
+ .def __fmul
+ .assume adl=1
+
+__fmul equ 000288h
diff --git a/frontends/calculator/CEdev/lib/shared/fpneg.src b/frontends/calculator/CEdev/lib/shared/fpneg.src index 9de1421..06e6643 100644 --- a/frontends/calculator/CEdev/lib/shared/fpneg.src +++ b/frontends/calculator/CEdev/lib/shared/fpneg.src @@ -1,32 +1,32 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; IEEE Negate. -; -; INPUTS: -; AuBC: 32-bit IEEE Single Precision. -; -; OUTPUTS: -; AuBC: 32-bit IEEE Single Precision. -; -;-------------------------------------------------------------- - .def __fneg - .assume adl=1 - -__fneg: - or a,a - jr nz,__noexit - push hl - sbc hl,hl - sbc hl,bc - pop hl - ret z -__noexit: - xor a,80h - ret +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; IEEE Negate.
+;
+; INPUTS:
+; AuBC: 32-bit IEEE Single Precision.
+;
+; OUTPUTS:
+; AuBC: 32-bit IEEE Single Precision.
+;
+;--------------------------------------------------------------
+ .def __fneg
+ .assume adl=1
+
+__fneg:
+ or a,a
+ jr nz,__noexit
+ push hl
+ sbc hl,hl
+ sbc hl,bc
+ pop hl
+ ret z
+__noexit:
+ xor a,80h
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/fppack.src b/frontends/calculator/CEdev/lib/shared/fppack.src index fe14285..6dad178 100644 --- a/frontends/calculator/CEdev/lib/shared/fppack.src +++ b/frontends/calculator/CEdev/lib/shared/fppack.src @@ -1,28 +1,28 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; Pack IEEE operand of dyadic operations. -; -; INPUTS: -; AuBC: 2s-comp mantissa+fraction (9+23 bit) -; E: Exponent. -; D: Sign. -; -; OUTPUTS: AuBC: 32 bit IEEE float. -; -; A AAAAAAB BBBBBBBBBBBBBBCCCCCCCCC -; S EEEEEEE FFFFFFFFFFFFFFFFFFFFFFF -; 0 1 8 9 31 -; MODIFIES: -; flags -;-------------------------------------------------------------- - .def __fppack - .assume adl=1 - -__fppack equ 00026Ch +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; Pack IEEE operand of dyadic operations.
+;
+; INPUTS:
+; AuBC: 2s-comp mantissa+fraction (9+23 bit)
+; E: Exponent.
+; D: Sign.
+;
+; OUTPUTS: AuBC: 32 bit IEEE float.
+;
+; A AAAAAAB BBBBBBBBBBBBBBCCCCCCCCC
+; S EEEEEEE FFFFFFFFFFFFFFFFFFFFFFF
+; 0 1 8 9 31
+; MODIFIES:
+; flags
+;--------------------------------------------------------------
+ .def __fppack
+ .assume adl=1
+
+__fppack equ 00026Ch
diff --git a/frontends/calculator/CEdev/lib/shared/fpsub.src b/frontends/calculator/CEdev/lib/shared/fpsub.src index daaf034..cefa0e3 100644 --- a/frontends/calculator/CEdev/lib/shared/fpsub.src +++ b/frontends/calculator/CEdev/lib/shared/fpsub.src @@ -1,27 +1,27 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; IEEE Single precision sub -; Input: -; Operand1: -; abc : 32 bit IEEE single precision -; -; Operand2: -; ehl : 32 bit IEEE single precision -; -; Output: -; Result: abc : 32 bit IEEE single precision (abc - ehl) -; Registers Used: - -;------------------------------------------------------------------------- - .def __fsub - .ref __fadd - .assume adl=1 - -__fsub equ 000290h +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; IEEE Single precision sub
+; Input:
+; Operand1:
+; abc : 32 bit IEEE single precision
+;
+; Operand2:
+; ehl : 32 bit IEEE single precision
+;
+; Output:
+; Result: abc : 32 bit IEEE single precision (abc - ehl)
+; Registers Used:
+
+;-------------------------------------------------------------------------
+ .def __fsub
+ .ref __fadd
+ .assume adl=1
+
+__fsub equ 000290h
diff --git a/frontends/calculator/CEdev/lib/shared/fpultof.src b/frontends/calculator/CEdev/lib/shared/fpultof.src index 45fe5f4..5a91730 100644 --- a/frontends/calculator/CEdev/lib/shared/fpultof.src +++ b/frontends/calculator/CEdev/lib/shared/fpultof.src @@ -1,22 +1,22 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; Unsigned long to IEEE Single precision. -; -; INPUTS: -; abc: 32-bit unsigned long -; -; OUTPUTS: -; abc: IEEE Single precision. -; -;-------------------------------------------------------------- - .def __ultof - .assume adl=1 - -__ultof equ 000280h +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; Unsigned long to IEEE Single precision.
+;
+; INPUTS:
+; abc: 32-bit unsigned long
+;
+; OUTPUTS:
+; abc: IEEE Single precision.
+;
+;--------------------------------------------------------------
+ .def __ultof
+ .assume adl=1
+
+__ultof equ 000280h
diff --git a/frontends/calculator/CEdev/lib/shared/fpupop1.src b/frontends/calculator/CEdev/lib/shared/fpupop1.src index 4a7064f..e0c623d 100644 --- a/frontends/calculator/CEdev/lib/shared/fpupop1.src +++ b/frontends/calculator/CEdev/lib/shared/fpupop1.src @@ -1,48 +1,48 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; Unpack IEEE op1 of dyadic operations. -; -; INPUTS: AuBC: 32bits -; -; A AAAAAAAB BBBBBBBBBBBBBBBCCCCCCCC -; S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF -; 0 1 8 9 31 -; -; OUTPUTS: uBC: Mantissa -; A: Exponent -; D: Sign Bit -; ZERO FLAG Set if op was zero. -; -; MODIFIES: -; flags -;-------------------------------------------------------------- - .def __fpupop1 - .assume adl=1 - -__fpupop1: - push ix - ld ix,0 - add ix,sp - push bc - rlc (ix-1) ;move high-bit to low-bit - scf - rr (ix-1) ;carry = exponent low-bit, high-bit = 1 - pop bc ;restore modified mantissa - rl a ;compute exponent, carry = sign - ld d,0 - jr nz,nzero ;skip if exponent non-zero - - ld bc,0 ;clear mantissa - or a,a ;clear carry -nzero: - rl d ;set 1 if negative operand - or a,a ;set Z/NZ - pop ix - ret +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; Unpack IEEE op1 of dyadic operations.
+;
+; INPUTS: AuBC: 32bits
+;
+; A AAAAAAAB BBBBBBBBBBBBBBBCCCCCCCC
+; S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF
+; 0 1 8 9 31
+;
+; OUTPUTS: uBC: Mantissa
+; A: Exponent
+; D: Sign Bit
+; ZERO FLAG Set if op was zero.
+;
+; MODIFIES:
+; flags
+;--------------------------------------------------------------
+ .def __fpupop1
+ .assume adl=1
+
+__fpupop1:
+ push ix
+ ld ix,0
+ add ix,sp
+ push bc
+ rlc (ix-1) ;move high-bit to low-bit
+ scf
+ rr (ix-1) ;carry = exponent low-bit, high-bit = 1
+ pop bc ;restore modified mantissa
+ rl a ;compute exponent, carry = sign
+ ld d,0
+ jr nz,nzero ;skip if exponent non-zero
+
+ ld bc,0 ;clear mantissa
+ or a,a ;clear carry
+nzero:
+ rl d ;set 1 if negative operand
+ or a,a ;set Z/NZ
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/fpupop2.src b/frontends/calculator/CEdev/lib/shared/fpupop2.src index 8461f59..e5e899b 100644 --- a/frontends/calculator/CEdev/lib/shared/fpupop2.src +++ b/frontends/calculator/CEdev/lib/shared/fpupop2.src @@ -1,47 +1,47 @@ -;-------------------------------------------------------------- -; -; Code Generation Helper -; For the Zilog eZ80 C Compiler -; Copyright 1992-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -;-------------------------------------------------------------- -; -; Unpack IEEE op2 of dyadic operations. -; -; INPUTS: EuHL: 32 bits -; -; E EEEEEEEH HHHHHHHHHHHHHHHLLLLLLLL -; S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF -; 0 1 8 9 31 -; -; OUTPUTS: uHL: Mantissa -; E: Exponent -; D: Sign Bit -; ZERO FLAG Set if op was zero. -; -; MODIFIES: -; flags -;-------------------------------------------------------------- - .def __fpupop2 - .assume adl=1 - -__fpupop2: - push bc - ld bc,0800000h - add hl,bc - jr nc,ncarry - add hl,bc - scf -ncarry: - ld d,c - pop bc - rl e - jr nz,nzero - or a,a - sbc hl,hl -nzero: - rl d - inc e - dec e - ret +;--------------------------------------------------------------
+;
+; Code Generation Helper
+; For the Zilog eZ80 C Compiler
+; Copyright 1992-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+; Unpack IEEE op2 of dyadic operations.
+;
+; INPUTS: EuHL: 32 bits
+;
+; E EEEEEEEH HHHHHHHHHHHHHHHLLLLLLLL
+; S EEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF
+; 0 1 8 9 31
+;
+; OUTPUTS: uHL: Mantissa
+; E: Exponent
+; D: Sign Bit
+; ZERO FLAG Set if op was zero.
+;
+; MODIFIES:
+; flags
+;--------------------------------------------------------------
+ .def __fpupop2
+ .assume adl=1
+
+__fpupop2:
+ push bc
+ ld bc,0800000h
+ add hl,bc
+ jr nc,ncarry
+ add hl,bc
+ scf
+ncarry:
+ ld d,c
+ pop bc
+ rl e
+ jr nz,nzero
+ or a,a
+ sbc hl,hl
+nzero:
+ rl d
+ inc e
+ dec e
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/frameset.src b/frontends/calculator/CEdev/lib/shared/frameset.src index 669a9d2..c9e7848 100644 --- a/frontends/calculator/CEdev/lib/shared/frameset.src +++ b/frontends/calculator/CEdev/lib/shared/frameset.src @@ -1,12 +1,12 @@ - .assume adl=1 - .def __frameset - -__frameset: - pop de - push ix - ld ix,0 - add ix,sp - add hl,sp - ld sp,hl - ex de,hl + .assume adl=1
+ .def __frameset
+
+__frameset:
+ pop de
+ push ix
+ ld ix,0
+ add ix,sp
+ add hl,sp
+ ld sp,hl
+ ex de,hl
jp (hl)
\ No newline at end of file diff --git a/frontends/calculator/CEdev/lib/shared/frameset0.src b/frontends/calculator/CEdev/lib/shared/frameset0.src index 061a597..d15c47e 100644 --- a/frontends/calculator/CEdev/lib/shared/frameset0.src +++ b/frontends/calculator/CEdev/lib/shared/frameset0.src @@ -1,9 +1,9 @@ - .assume adl=1 - .def __frameset0 - -__frameset0: - pop hl - push ix - ld ix,0 - add ix,sp + .assume adl=1
+ .def __frameset0
+
+__frameset0:
+ pop hl
+ push ix
+ ld ix,0
+ add ix,sp
jp (hl)
\ No newline at end of file diff --git a/frontends/calculator/CEdev/lib/shared/frbmuls.src b/frontends/calculator/CEdev/lib/shared/frbmuls.src index c415d42..3897459 100644 --- a/frontends/calculator/CEdev/lib/shared/frbmuls.src +++ b/frontends/calculator/CEdev/lib/shared/frbmuls.src @@ -1,53 +1,53 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract short Multiplication signed. -; -; Input: -; Operand1: -; H : 8 bits -; -; Operand2: -; L : 8 bits -; -; Output: -; Result: A : 8 bits -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frbmuls - .assume adl=1 - -__frbmuls: - push hl - ;; - ;; Check sign info - ;; - xor a,a - rl h - jr nc,_L0 - sub a,h - ld h,a -_L0: - xor a,a - rl l - jr nc,_L1 - sub a,l - ld l,a -_L1: - mlt hl - ld a,h - pop hl - or a,a - rra - adc a,0h - push af - ld a,h - xor a,l - jp p,_L2 - pop af - neg - ret -_L2: - pop af - ret - +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract short Multiplication signed.
+;
+; Input:
+; Operand1:
+; H : 8 bits
+;
+; Operand2:
+; L : 8 bits
+;
+; Output:
+; Result: A : 8 bits
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frbmuls
+ .assume adl=1
+
+__frbmuls:
+ push hl
+ ;;
+ ;; Check sign info
+ ;;
+ xor a,a
+ rl h
+ jr nc,_L0
+ sub a,h
+ ld h,a
+_L0:
+ xor a,a
+ rl l
+ jr nc,_L1
+ sub a,l
+ ld l,a
+_L1:
+ mlt hl
+ ld a,h
+ pop hl
+ or a,a
+ rra
+ adc a,0h
+ push af
+ ld a,h
+ xor a,l
+ jp p,_L2
+ pop af
+ neg
+ ret
+_L2:
+ pop af
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/frbtof.src b/frontends/calculator/CEdev/lib/shared/frbtof.src index 1967abb..7d9f158 100644 --- a/frontends/calculator/CEdev/lib/shared/frbtof.src +++ b/frontends/calculator/CEdev/lib/shared/frbtof.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract unsigned char to float conversion. -; -; Input: -; Operand1: -; A : 8 bits -; -; Output: -; Result: eHL : 32 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frbtof - .assume adl=1 - -__frbtof equ 00029Ch +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract unsigned char to float conversion.
+;
+; Input:
+; Operand1:
+; A : 8 bits
+;
+; Output:
+; Result: eHL : 32 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frbtof
+ .assume adl=1
+
+__frbtof equ 00029Ch
diff --git a/frontends/calculator/CEdev/lib/shared/frftob.src b/frontends/calculator/CEdev/lib/shared/frftob.src index 39065d8..99cb225 100644 --- a/frontends/calculator/CEdev/lib/shared/frftob.src +++ b/frontends/calculator/CEdev/lib/shared/frftob.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; float to fract char conversion. -; -; Input: -; Operand1: -; eHL : 32 bits -; -; Output: -; Result: A : 8 bits -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frftob - .assume adl=1 - -__frftob equ 0002A0h +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; float to fract char conversion.
+;
+; Input:
+; Operand1:
+; eHL : 32 bits
+;
+; Output:
+; Result: A : 8 bits
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frftob
+ .assume adl=1
+
+__frftob equ 0002A0h
diff --git a/frontends/calculator/CEdev/lib/shared/frftoi.src b/frontends/calculator/CEdev/lib/shared/frftoi.src index 048c298..6f4706d 100644 --- a/frontends/calculator/CEdev/lib/shared/frftoi.src +++ b/frontends/calculator/CEdev/lib/shared/frftoi.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; float to fract integer conversion. -; -; Input: -; Operand1: -; eHL : 32 bits -; -; Output: -; Result: HL : 24 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frftoi - .assume adl=1 - -__frftoi equ 0002A8h +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; float to fract integer conversion.
+;
+; Input:
+; Operand1:
+; eHL : 32 bits
+;
+; Output:
+; Result: HL : 24 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frftoi
+ .assume adl=1
+
+__frftoi equ 0002A8h
diff --git a/frontends/calculator/CEdev/lib/shared/frftos.src b/frontends/calculator/CEdev/lib/shared/frftos.src index b2f71b1..17f1bcb 100644 --- a/frontends/calculator/CEdev/lib/shared/frftos.src +++ b/frontends/calculator/CEdev/lib/shared/frftos.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; float to fract short conversion. -; -; Input: -; Operand1: -; eHL : 32 bits -; -; Output: -; Result: HL : 16 bits -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frftos - .assume adl=1 - -__frftos equ 0002B0h +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; float to fract short conversion.
+;
+; Input:
+; Operand1:
+; eHL : 32 bits
+;
+; Output:
+; Result: HL : 16 bits
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frftos
+ .assume adl=1
+
+__frftos equ 0002B0h
diff --git a/frontends/calculator/CEdev/lib/shared/frftoub.src b/frontends/calculator/CEdev/lib/shared/frftoub.src index e07b750..da46faf 100644 --- a/frontends/calculator/CEdev/lib/shared/frftoub.src +++ b/frontends/calculator/CEdev/lib/shared/frftoub.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; float to fract unsigned char conversion. -; -; Input: -; Operand1: -; eHL : 32 bits -; -; Output: -; Result: A : 8 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frftoub - .assume adl=1 - -__frftoub equ 0002A4h +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; float to fract unsigned char conversion.
+;
+; Input:
+; Operand1:
+; eHL : 32 bits
+;
+; Output:
+; Result: A : 8 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frftoub
+ .assume adl=1
+
+__frftoub equ 0002A4h
diff --git a/frontends/calculator/CEdev/lib/shared/frftoui.src b/frontends/calculator/CEdev/lib/shared/frftoui.src index 07ef9c0..0136f56 100644 --- a/frontends/calculator/CEdev/lib/shared/frftoui.src +++ b/frontends/calculator/CEdev/lib/shared/frftoui.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; float to fract unsigned integer conversion. -; -; Input: -; Operand1: -; eHL : 32 bits -; -; Output: -; Result: HL : 24 bits -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frftoui - .assume adl=1 - -__frftoui equ 0002ACh +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; float to fract unsigned integer conversion.
+;
+; Input:
+; Operand1:
+; eHL : 32 bits
+;
+; Output:
+; Result: HL : 24 bits
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frftoui
+ .assume adl=1
+
+__frftoui equ 0002ACh
diff --git a/frontends/calculator/CEdev/lib/shared/frftous.src b/frontends/calculator/CEdev/lib/shared/frftous.src index 0fbb6b2..12b743e 100644 --- a/frontends/calculator/CEdev/lib/shared/frftous.src +++ b/frontends/calculator/CEdev/lib/shared/frftous.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; float to fract unsigned short conversion. -; -; Input: -; Operand1: -; eHL : 32 bits -; -; Output: -; Result: HL : 16 bits -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frftous - .assume adl=1 - -__frftous equ 0002B4h +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; float to fract unsigned short conversion.
+;
+; Input:
+; Operand1:
+; eHL : 32 bits
+;
+; Output:
+; Result: HL : 16 bits
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frftous
+ .assume adl=1
+
+__frftous equ 0002B4h
diff --git a/frontends/calculator/CEdev/lib/shared/frimuls.src b/frontends/calculator/CEdev/lib/shared/frimuls.src index 955d658..bc886a5 100644 --- a/frontends/calculator/CEdev/lib/shared/frimuls.src +++ b/frontends/calculator/CEdev/lib/shared/frimuls.src @@ -1,81 +1,81 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract interger Multiplication Unsigned. -; -; Input: -; Operand1: -; uHL : 24 bits -; -; Operand2: -; uBC : 24 bits -; -; Output: -; Result: uHL : 24 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .assume adl=1 - .def __frimuls - .ref __frimulu - -__frimuls: - push af - push de - push bc - push hl - ;; - ;; Check sign info - ;; - add hl,hl - jr nc,_L0 - ex de,hl - or a,a - sbc hl,hl - sbc hl,de -_L0: - ex de,hl - or a,a - sbc hl,hl - add hl,bc - add hl,hl - jr nc,_L1 - or a,a - sbc hl,hl - sbc hl,bc - add hl,hl -_L1: - ld bc,hl - ex de,hl - call __frimulu - push hl - ex de,hl - ld hl,2 - add hl,sp - rr (hl) - rr d - rr e - pop hl - ld h,d - ld l,e - ;; - ;; Check signs - ;; - ex de,hl - ld hl,2 - add hl,sp - ld a,(hl) - inc hl - ld sp,hl - inc hl - inc hl - xor a,(hl) - jp p,_L2 - sbc hl,hl - sbc hl,de - ex de,hl -_L2: - ex de,hl - pop bc - pop de - pop af - ret +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract interger Multiplication Unsigned.
+;
+; Input:
+; Operand1:
+; uHL : 24 bits
+;
+; Operand2:
+; uBC : 24 bits
+;
+; Output:
+; Result: uHL : 24 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .assume adl=1
+ .def __frimuls
+ .ref __frimulu
+
+__frimuls:
+ push af
+ push de
+ push bc
+ push hl
+ ;;
+ ;; Check sign info
+ ;;
+ add hl,hl
+ jr nc,_L0
+ ex de,hl
+ or a,a
+ sbc hl,hl
+ sbc hl,de
+_L0:
+ ex de,hl
+ or a,a
+ sbc hl,hl
+ add hl,bc
+ add hl,hl
+ jr nc,_L1
+ or a,a
+ sbc hl,hl
+ sbc hl,bc
+ add hl,hl
+_L1:
+ ld bc,hl
+ ex de,hl
+ call __frimulu
+ push hl
+ ex de,hl
+ ld hl,2
+ add hl,sp
+ rr (hl)
+ rr d
+ rr e
+ pop hl
+ ld h,d
+ ld l,e
+ ;;
+ ;; Check signs
+ ;;
+ ex de,hl
+ ld hl,2
+ add hl,sp
+ ld a,(hl)
+ inc hl
+ ld sp,hl
+ inc hl
+ inc hl
+ xor a,(hl)
+ jp p,_L2
+ sbc hl,hl
+ sbc hl,de
+ ex de,hl
+_L2:
+ ex de,hl
+ pop bc
+ pop de
+ pop af
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/frimulu.src b/frontends/calculator/CEdev/lib/shared/frimulu.src index d008a49..1f95434 100644 --- a/frontends/calculator/CEdev/lib/shared/frimulu.src +++ b/frontends/calculator/CEdev/lib/shared/frimulu.src @@ -1,112 +1,112 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract interger Multiplication Unsigned. -; -; Input: -; Operand1: -; uHL : 24 bits -; -; Operand2: -; uBC : 24 bits -; -; Output: -; Result: uHL : 24 bits -; Registers Used: -; none -;------------------------------------------------------------------------- - .assume adl=1 - .def __frimulu - -__frimulu: - push af - push de - push iy - push bc - push hl - ld d,l - ld e,c - mlt de - ld a,d - ld d,h - ld e,b - ld b,h - ld h,e - mlt hl - mlt bc - mlt de - add a,c - ld c,a - ld a,b - adc a,0h - ld b,a - add.s hl,bc - jr nc,_L0 - inc d -_L0: - ld iy,0h - add iy,sp - ld b,(iy+2) - ld c,(iy+5) - mlt bc - ld a,h - add a,e - ld e,a - jr nc,_L1 - inc d - jr nz,_L1 - inc bc -_L1: - ld h,(iy+2) - ld l,(iy+3) - mlt hl - - ld a,l ;approximation - add a,80h - ld l,a - ld a,h - adc a,0h - ld h,a - - add.s hl,de - jr nc,_L2 - inc bc -_L2: - ld d,(iy+0) - ld e,(iy+5) - mlt de - add.s hl,de - jr nc,_L3 - inc bc -_L3: - ld a,h - ld d,(iy+2) - ld e,(iy+4) - ld h,(iy+1) - ld l,(iy+5) - mlt de - mlt hl - add.s hl,de - jr nc,_L4 - inc b -_L4: - add a,l - ld l,a - ld a,h - adc a,c - ld h,a - jr nc,_L5 - inc b -_L5: - ex de,hl - push bc - dec sp - pop hl - inc sp - ld h,d - ld l,e - pop bc - pop bc - pop iy - pop de - pop af - ret +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract interger Multiplication Unsigned.
+;
+; Input:
+; Operand1:
+; uHL : 24 bits
+;
+; Operand2:
+; uBC : 24 bits
+;
+; Output:
+; Result: uHL : 24 bits
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .assume adl=1
+ .def __frimulu
+
+__frimulu:
+ push af
+ push de
+ push iy
+ push bc
+ push hl
+ ld d,l
+ ld e,c
+ mlt de
+ ld a,d
+ ld d,h
+ ld e,b
+ ld b,h
+ ld h,e
+ mlt hl
+ mlt bc
+ mlt de
+ add a,c
+ ld c,a
+ ld a,b
+ adc a,0h
+ ld b,a
+ add.s hl,bc
+ jr nc,_L0
+ inc d
+_L0:
+ ld iy,0h
+ add iy,sp
+ ld b,(iy+2)
+ ld c,(iy+5)
+ mlt bc
+ ld a,h
+ add a,e
+ ld e,a
+ jr nc,_L1
+ inc d
+ jr nz,_L1
+ inc bc
+_L1:
+ ld h,(iy+2)
+ ld l,(iy+3)
+ mlt hl
+
+ ld a,l ;approximation
+ add a,80h
+ ld l,a
+ ld a,h
+ adc a,0h
+ ld h,a
+
+ add.s hl,de
+ jr nc,_L2
+ inc bc
+_L2:
+ ld d,(iy+0)
+ ld e,(iy+5)
+ mlt de
+ add.s hl,de
+ jr nc,_L3
+ inc bc
+_L3:
+ ld a,h
+ ld d,(iy+2)
+ ld e,(iy+4)
+ ld h,(iy+1)
+ ld l,(iy+5)
+ mlt de
+ mlt hl
+ add.s hl,de
+ jr nc,_L4
+ inc b
+_L4:
+ add a,l
+ ld l,a
+ ld a,h
+ adc a,c
+ ld h,a
+ jr nc,_L5
+ inc b
+_L5:
+ ex de,hl
+ push bc
+ dec sp
+ pop hl
+ inc sp
+ ld h,d
+ ld l,e
+ pop bc
+ pop bc
+ pop iy
+ pop de
+ pop af
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/fritof.src b/frontends/calculator/CEdev/lib/shared/fritof.src index d35fb32..fddf7ab 100644 --- a/frontends/calculator/CEdev/lib/shared/fritof.src +++ b/frontends/calculator/CEdev/lib/shared/fritof.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract integer to float conversion. -; -; Input: -; Operand1: -; HL : 24 bits -; -; Output: -; Result: eHL : 32 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __fritof - .assume adl=1 - -__fritof equ 0002B8h +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract integer to float conversion.
+;
+; Input:
+; Operand1:
+; HL : 24 bits
+;
+; Output:
+; Result: eHL : 32 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __fritof
+ .assume adl=1
+
+__fritof equ 0002B8h
diff --git a/frontends/calculator/CEdev/lib/shared/frsmuls.src b/frontends/calculator/CEdev/lib/shared/frsmuls.src index b337a01..fb0e389 100644 --- a/frontends/calculator/CEdev/lib/shared/frsmuls.src +++ b/frontends/calculator/CEdev/lib/shared/frsmuls.src @@ -1,61 +1,61 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract short Multiplication signed. -; -; Input: -; Operand1: -; HL : 16 bits -; -; Operand2: -; BC : 16 bits -; -; Output: -; Result: HL : 16 bits -; Registers Used: -; none -;------------------------------------------------------------------------- - .assume adl=1 - .def __frsmuls - .ref __frsmulu - -__frsmuls: - push af - push de - push bc - push hl - ;; - ;; Check sign info - ;; - add.s hl,hl - jr nc,_L0 - ex de,hl - or a,a - sbc hl,hl - sbc hl,de -_L0: - rl c - rl b - jr nc,_L1 - ex de,hl - or a,a - sbc hl,hl - sbc hl,bc - ld b,h - ld c,l - ex de,hl -_L1: - call __frsmulu - srl h - rr l - pop af - pop bc - xor a,b - jp p,_L2 - ex de,hl - sbc hl,hl - sbc hl,de -_L2: - pop de - pop af - ret - +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract short Multiplication signed.
+;
+; Input:
+; Operand1:
+; HL : 16 bits
+;
+; Operand2:
+; BC : 16 bits
+;
+; Output:
+; Result: HL : 16 bits
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .assume adl=1
+ .def __frsmuls
+ .ref __frsmulu
+
+__frsmuls:
+ push af
+ push de
+ push bc
+ push hl
+ ;;
+ ;; Check sign info
+ ;;
+ add.s hl,hl
+ jr nc,_L0
+ ex de,hl
+ or a,a
+ sbc hl,hl
+ sbc hl,de
+_L0:
+ rl c
+ rl b
+ jr nc,_L1
+ ex de,hl
+ or a,a
+ sbc hl,hl
+ sbc hl,bc
+ ld b,h
+ ld c,l
+ ex de,hl
+_L1:
+ call __frsmulu
+ srl h
+ rr l
+ pop af
+ pop bc
+ xor a,b
+ jp p,_L2
+ ex de,hl
+ sbc hl,hl
+ sbc hl,de
+_L2:
+ pop de
+ pop af
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/frsmulu.src b/frontends/calculator/CEdev/lib/shared/frsmulu.src index ca9e7f6..30ee909 100644 --- a/frontends/calculator/CEdev/lib/shared/frsmulu.src +++ b/frontends/calculator/CEdev/lib/shared/frsmulu.src @@ -1,51 +1,51 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract interger Multiplication Unsigned. -; -; Input: -; Operand1: -; HL : 16 bits -; -; Operand2: -; BC : 16 bits -; -; Output: -; Result: HL : 16 bits -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frsmulu - .assume adl=1 - -__frsmulu: - push af - push de - push bc - ld d,l - ld e,c - mlt de - ld a,d - ld d,h - ld e,b - ld b,h - ld h,e - mlt hl - mlt bc - mlt de - add a,c - jr nc,_L0 - inc de -_L0: - ld c,a - xor a,a - add hl,bc - adc a,d - ld d,a - ld l,h - ld h,0h - ex de,hl - add hl,de - pop bc - pop de - pop af - ret +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract interger Multiplication Unsigned.
+;
+; Input:
+; Operand1:
+; HL : 16 bits
+;
+; Operand2:
+; BC : 16 bits
+;
+; Output:
+; Result: HL : 16 bits
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frsmulu
+ .assume adl=1
+
+__frsmulu:
+ push af
+ push de
+ push bc
+ ld d,l
+ ld e,c
+ mlt de
+ ld a,d
+ ld d,h
+ ld e,b
+ ld b,h
+ ld h,e
+ mlt hl
+ mlt bc
+ mlt de
+ add a,c
+ jr nc,_L0
+ inc de
+_L0:
+ ld c,a
+ xor a,a
+ add hl,bc
+ adc a,d
+ ld d,a
+ ld l,h
+ ld h,0h
+ ex de,hl
+ add hl,de
+ pop bc
+ pop de
+ pop af
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/frstof.src b/frontends/calculator/CEdev/lib/shared/frstof.src index a5e8003..03f0f56 100644 --- a/frontends/calculator/CEdev/lib/shared/frstof.src +++ b/frontends/calculator/CEdev/lib/shared/frstof.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract short to float conversion. -; -; Input: -; Operand1: -; HL : 24 bits -; -; Output: -; Result: eHL : 32 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frstof - .assume adl=1 - -__frstof equ 0002C0h +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract short to float conversion.
+;
+; Input:
+; Operand1:
+; HL : 24 bits
+;
+; Output:
+; Result: eHL : 32 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frstof
+ .assume adl=1
+
+__frstof equ 0002C0h
diff --git a/frontends/calculator/CEdev/lib/shared/frubtof.src b/frontends/calculator/CEdev/lib/shared/frubtof.src index 7a2a234..e4e6511 100644 --- a/frontends/calculator/CEdev/lib/shared/frubtof.src +++ b/frontends/calculator/CEdev/lib/shared/frubtof.src @@ -1,17 +1,17 @@ -; (c) Copyright 2004-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract unsigned char to float conversion. -; -; Input: -; Operand1: -; A : 8 bits -; -; Output: -; Result: eHL : 32 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frubtof - .assume adl=1 - -__frubtof equ 0002C4h +; (c) Copyright 2004-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract unsigned char to float conversion.
+;
+; Input:
+; Operand1:
+; A : 8 bits
+;
+; Output:
+; Result: eHL : 32 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frubtof
+ .assume adl=1
+
+__frubtof equ 0002C4h
diff --git a/frontends/calculator/CEdev/lib/shared/fruitof.src b/frontends/calculator/CEdev/lib/shared/fruitof.src index a173276..2726889 100644 --- a/frontends/calculator/CEdev/lib/shared/fruitof.src +++ b/frontends/calculator/CEdev/lib/shared/fruitof.src @@ -1,17 +1,17 @@ -; (c) Copyright 2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract unsigned integer to float conversion. -; -; Input: -; Operand1: -; HL : 24 bits -; -; Output: -; Result: eHL : 32 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __fruitof - .assume adl=1 - -__fruitof equ 0002BCh +; (c) Copyright 2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract unsigned integer to float conversion.
+;
+; Input:
+; Operand1:
+; HL : 24 bits
+;
+; Output:
+; Result: eHL : 32 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __fruitof
+ .assume adl=1
+
+__fruitof equ 0002BCh
diff --git a/frontends/calculator/CEdev/lib/shared/frustof.src b/frontends/calculator/CEdev/lib/shared/frustof.src index 4cf0ba8..9b10c57 100644 --- a/frontends/calculator/CEdev/lib/shared/frustof.src +++ b/frontends/calculator/CEdev/lib/shared/frustof.src @@ -1,17 +1,17 @@ -; (c) Copyright 2008 Zilog, Inc. -;------------------------------------------------------------------------- -; fract unsigned short to float conversion. -; -; Input: -; Operand1: -; HL : 16 bits -; -; Output: -; Result: eHL : 32 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __frustof - .assume adl=1 - -__frustof equ 0002C8h +; (c) Copyright 2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; fract unsigned short to float conversion.
+;
+; Input:
+; Operand1:
+; HL : 16 bits
+;
+; Output:
+; Result: eHL : 32 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __frustof
+ .assume adl=1
+
+__frustof equ 0002C8h
diff --git a/frontends/calculator/CEdev/lib/shared/getstringinput.src b/frontends/calculator/CEdev/lib/shared/getstringinput.src index b3282c3..d29028e 100644 --- a/frontends/calculator/CEdev/lib/shared/getstringinput.src +++ b/frontends/calculator/CEdev/lib/shared/getstringinput.src @@ -1,136 +1,136 @@ -; --- -; void os_GetStringInput(char *string, char *buf, size_t size) -; --- - - .def _os_GetStringInput - .assume adl=1 - -kUp := 3 -kLeft := 2 -kDown := 4 -kEnter := 5 -kClear := 9 -kRight := 1 -curLock := 4 -flags := $D00080 -curRow := $D00595 -curUnder := $D00599 -_PutS := $207C0 -_PutC := $207B8 -_PutPS := $207C8 -_GetKey := $20D8C -_CursorOn := $208B0 -_CursorOff := $208A8 -_PullDownChk := $208BC -_ConvKeyToTok := $20E40 -_GetTokString := $20874 -_PutTokString := $20D74 - -_os_GetStringInput: - push ix - ld ix,0 - add ix,sp - ld hl,(ix+6) ; hl -> input string prompt - add hl,de - xor a,a - sbc hl,de - jr z,__nodisp - ld iy,flags - call _PutS -__nodisp: - ld hl,(curRow) - ld (__savecur),hl - ld a,(ix+12) - dec a - ld (ix+12),a - ld (ix+6),a -__start: - ld de,(ix+9) -__loop: - ld a,' ' - ld (curUnder),a - push de - push ix - call _CursorOn -__getkey: - call _GetKey - call _CursorOff - call _PullDownChk - call _CursorOn - jr c,__getkey - cp a,kLeft - jr z,__loop - cp a,kDown - jr z,__loop - cp a,kRight - jr z,__loop - cp a,kUp - jr z,__loop - cp a,kClear - jr z,__clearpop - cp a,kEnter - jr z,__done - call _ConvKeyToTok - call _GetTokString - pop ix - pop de - ld b,(hl) - inc hl - ld a,(ix+12) - sub a,b - jr nc,__notfull - ld b,(ix+12) - xor a,a -__notfull: - ld (ix+12),a -__draw: - ld a,(hl) - ld (de),a - inc hl - inc de - call _PutC - djnz __draw - ld a,(ix+12) - or a,a - jr nz,__loop -__full: - ld a,' ' - ld (curUnder),a - call _GetKey - cp a,kClear - jr z,__clear - cp a,kEnter - jr z,__exit - jr __full -__clearpop: - pop ix - pop de -__clear: -__savecur := $+1 - ld hl,0 - ld (curRow),hl - ld a,(ix+6) - ld b,(ix+12) - ld (ix+12),a - sub a,b - ld b,a - inc b -__clearloop: - ld a,' ' - call _PutC - djnz __clearloop - ld hl,(__savecur) - ld (curRow),hl - jr __start -__done: - pop ix - pop de -__exit: - ld a,' ' - ld (curUnder),a - xor a,a - ld (de),a - call _CursorOff - di - pop ix - ret +; ---
+; void os_GetStringInput(char *string, char *buf, size_t size)
+; ---
+
+ .def _os_GetStringInput
+ .assume adl=1
+
+kUp := 3
+kLeft := 2
+kDown := 4
+kEnter := 5
+kClear := 9
+kRight := 1
+curLock := 4
+flags := $D00080
+curRow := $D00595
+curUnder := $D00599
+_PutS := $207C0
+_PutC := $207B8
+_PutPS := $207C8
+_GetKey := $20D8C
+_CursorOn := $208B0
+_CursorOff := $208A8
+_PullDownChk := $208BC
+_ConvKeyToTok := $20E40
+_GetTokString := $20874
+_PutTokString := $20D74
+
+_os_GetStringInput:
+ push ix
+ ld ix,0
+ add ix,sp
+ ld hl,(ix+6) ; hl -> input string prompt
+ add hl,de
+ xor a,a
+ sbc hl,de
+ jr z,__nodisp
+ ld iy,flags
+ call _PutS
+__nodisp:
+ ld hl,(curRow)
+ ld (__savecur),hl
+ ld a,(ix+12)
+ dec a
+ ld (ix+12),a
+ ld (ix+6),a
+__start:
+ ld de,(ix+9)
+__loop:
+ ld a,' '
+ ld (curUnder),a
+ push de
+ push ix
+ call _CursorOn
+__getkey:
+ call _GetKey
+ call _CursorOff
+ call _PullDownChk
+ call _CursorOn
+ jr c,__getkey
+ cp a,kLeft
+ jr z,__loop
+ cp a,kDown
+ jr z,__loop
+ cp a,kRight
+ jr z,__loop
+ cp a,kUp
+ jr z,__loop
+ cp a,kClear
+ jr z,__clearpop
+ cp a,kEnter
+ jr z,__done
+ call _ConvKeyToTok
+ call _GetTokString
+ pop ix
+ pop de
+ ld b,(hl)
+ inc hl
+ ld a,(ix+12)
+ sub a,b
+ jr nc,__notfull
+ ld b,(ix+12)
+ xor a,a
+__notfull:
+ ld (ix+12),a
+__draw:
+ ld a,(hl)
+ ld (de),a
+ inc hl
+ inc de
+ call _PutC
+ djnz __draw
+ ld a,(ix+12)
+ or a,a
+ jr nz,__loop
+__full:
+ ld a,' '
+ ld (curUnder),a
+ call _GetKey
+ cp a,kClear
+ jr z,__clear
+ cp a,kEnter
+ jr z,__exit
+ jr __full
+__clearpop:
+ pop ix
+ pop de
+__clear:
+__savecur := $+1
+ ld hl,0
+ ld (curRow),hl
+ ld a,(ix+6)
+ ld b,(ix+12)
+ ld (ix+12),a
+ sub a,b
+ ld b,a
+ inc b
+__clearloop:
+ ld a,' '
+ call _PutC
+ djnz __clearloop
+ ld hl,(__savecur)
+ ld (curRow),hl
+ jr __start
+__done:
+ pop ix
+ pop de
+__exit:
+ ld a,' '
+ ld (curUnder),a
+ xor a,a
+ ld (de),a
+ call _CursorOff
+ di
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/iand.src b/frontends/calculator/CEdev/lib/shared/iand.src index 79d731c..0ddf272 100644 --- a/frontends/calculator/CEdev/lib/shared/iand.src +++ b/frontends/calculator/CEdev/lib/shared/iand.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer AND. -; Input: -; Operand1: -; hl : 24 bit -; -; Operand2: -; bc : 24 bit -; -; Output: -; Result: hl : 24 bit -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __iand - .assume adl=1 - -__iand equ 000134h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer AND.
+; Input:
+; Operand1:
+; hl : 24 bit
+;
+; Operand2:
+; bc : 24 bit
+;
+; Output:
+; Result: hl : 24 bit
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __iand
+ .assume adl=1
+
+__iand equ 000134h
diff --git a/frontends/calculator/CEdev/lib/shared/icmpzero.src b/frontends/calculator/CEdev/lib/shared/icmpzero.src index fced974..d264461 100644 --- a/frontends/calculator/CEdev/lib/shared/icmpzero.src +++ b/frontends/calculator/CEdev/lib/shared/icmpzero.src @@ -1,20 +1,20 @@ -; (c) Copyright 2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Set flag for comparison of 24-bit scalar with constant value zero -; Input: -; Operand1: HL register -; -; Output: -; Result: f register -; -; Registers Used: -; None -;------------------------------------------------------------------------- - .def __icmpzero - .assume adl=1 - -__icmpzero: - add hl,de - or a,a - sbc hl,de - ret +; (c) Copyright 2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Set flag for comparison of 24-bit scalar with constant value zero
+; Input:
+; Operand1: HL register
+;
+; Output:
+; Result: f register
+;
+; Registers Used:
+; None
+;-------------------------------------------------------------------------
+ .def __icmpzero
+ .assume adl=1
+
+__icmpzero:
+ add hl,de
+ or a,a
+ sbc hl,de
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/idivs.src b/frontends/calculator/CEdev/lib/shared/idivs.src index 1c7bba1..a52e712 100644 --- a/frontends/calculator/CEdev/lib/shared/idivs.src +++ b/frontends/calculator/CEdev/lib/shared/idivs.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Signed Integer Division -; Input: -; Operand1: -; hl : 24 bits (dividend x) -; -; Operand2: -; bc : 24 bits (divisor y) -; -; Output: -; Result: hl : 24 bits -; -; Registers Used: -; a, de -;------------------------------------------------------------------------- - .def __idivs - .assume adl=1 - -__idivs equ 00013Ch +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Signed Integer Division
+; Input:
+; Operand1:
+; hl : 24 bits (dividend x)
+;
+; Operand2:
+; bc : 24 bits (divisor y)
+;
+; Output:
+; Result: hl : 24 bits
+;
+; Registers Used:
+; a, de
+;-------------------------------------------------------------------------
+ .def __idivs
+ .assume adl=1
+
+__idivs equ 00013Ch
diff --git a/frontends/calculator/CEdev/lib/shared/idivu.src b/frontends/calculator/CEdev/lib/shared/idivu.src index 6fdcacc..6db78cf 100644 --- a/frontends/calculator/CEdev/lib/shared/idivu.src +++ b/frontends/calculator/CEdev/lib/shared/idivu.src @@ -1,21 +1,21 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Unsigned Integer Division. -; Input: -; Operand1: -; uHL : 24 bit dividend -; -; Operand2: -; uBC : 24 bit divisor -; -; Output: -; Result: uHL: 24 bit quotient -; -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __idivu,__idvrmu - .assume adl=1 - -__idivu equ 000140h -__idvrmu equ 000144h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Unsigned Integer Division.
+; Input:
+; Operand1:
+; uHL : 24 bit dividend
+;
+; Operand2:
+; uBC : 24 bit divisor
+;
+; Output:
+; Result: uHL: 24 bit quotient
+;
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __idivu,__idvrmu
+ .assume adl=1
+
+__idivu equ 000140h
+__idvrmu equ 000144h
diff --git a/frontends/calculator/CEdev/lib/shared/ildix.src b/frontends/calculator/CEdev/lib/shared/ildix.src index 8702ff5..e6523cc 100644 --- a/frontends/calculator/CEdev/lib/shared/ildix.src +++ b/frontends/calculator/CEdev/lib/shared/ildix.src @@ -1,17 +1,17 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer load hl,(ix+nnnnnn) -; Input: -; Operand1: -; BC : 24-bit offset from ix -; -; Output: -; Result: hl : 24 bit -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __ildix - .assume adl=1 - -__ildix equ 000148h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer load hl,(ix+nnnnnn)
+; Input:
+; Operand1:
+; BC : 24-bit offset from ix
+;
+; Output:
+; Result: hl : 24 bit
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __ildix
+ .assume adl=1
+
+__ildix equ 000148h
diff --git a/frontends/calculator/CEdev/lib/shared/ildiy.src b/frontends/calculator/CEdev/lib/shared/ildiy.src index 3883f15..07a02f2 100644 --- a/frontends/calculator/CEdev/lib/shared/ildiy.src +++ b/frontends/calculator/CEdev/lib/shared/ildiy.src @@ -1,17 +1,17 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer load hl,(iy+nnnnnn) -; Input: -; Operand1: -; BC : 24-bit offset from iy -; -; Output: -; Result: hl : 24 bit -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __ildiy - .assume adl=1 - -__ildiy equ 00014Ch +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer load hl,(iy+nnnnnn)
+; Input:
+; Operand1:
+; BC : 24-bit offset from iy
+;
+; Output:
+; Result: hl : 24 bit
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __ildiy
+ .assume adl=1
+
+__ildiy equ 00014Ch
diff --git a/frontends/calculator/CEdev/lib/shared/imuls.src b/frontends/calculator/CEdev/lib/shared/imuls.src index 6d70bc3..c67ab51 100644 --- a/frontends/calculator/CEdev/lib/shared/imuls.src +++ b/frontends/calculator/CEdev/lib/shared/imuls.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer Multiplication Signed. -; Input: -; Operand1: -; BC : 24 bits -; -; Operand2: -; HL : 24 bits -; -; Output: -; Result: hl : 24 bit -; Registers Used: -; de,af -;------------------------------------------------------------------------- - .def __imuls - .assume adl=1 - -__imuls equ 000154h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer Multiplication Signed.
+; Input:
+; Operand1:
+; BC : 24 bits
+;
+; Operand2:
+; HL : 24 bits
+;
+; Output:
+; Result: hl : 24 bit
+; Registers Used:
+; de,af
+;-------------------------------------------------------------------------
+ .def __imuls
+ .assume adl=1
+
+__imuls equ 000154h
diff --git a/frontends/calculator/CEdev/lib/shared/imulu.src b/frontends/calculator/CEdev/lib/shared/imulu.src index fd9c068..061efe2 100644 --- a/frontends/calculator/CEdev/lib/shared/imulu.src +++ b/frontends/calculator/CEdev/lib/shared/imulu.src @@ -1,24 +1,24 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer Multiplication Unsigned. -; Note: When multipying two n-bit values, the low-order n-bits -; of the product are the same, whether or not the values -; are considered signed or unsigned. -; Input: -; Operand1: -; uHL : 24 bits -; -; Operand2: -; uBC : 24 bits -; -; Output: -; Result: uHL : 24 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __imulu,__imul_b - .assume adl=1 - -__imul_b equ 000150h -__imulu equ 000158h - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer Multiplication Unsigned.
+; Note: When multipying two n-bit values, the low-order n-bits
+; of the product are the same, whether or not the values
+; are considered signed or unsigned.
+; Input:
+; Operand1:
+; uHL : 24 bits
+;
+; Operand2:
+; uBC : 24 bits
+;
+; Output:
+; Result: uHL : 24 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __imulu,__imul_b
+ .assume adl=1
+
+__imul_b equ 000150h
+__imulu equ 000158h
+
diff --git a/frontends/calculator/CEdev/lib/shared/indcall.src b/frontends/calculator/CEdev/lib/shared/indcall.src index 5f5a122..d8c8ea5 100644 --- a/frontends/calculator/CEdev/lib/shared/indcall.src +++ b/frontends/calculator/CEdev/lib/shared/indcall.src @@ -1,14 +1,14 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Indirect Call -; Input: -; Operand1: -; iy : 24 bit -; -; Output: -; Registers Used: -;------------------------------------------------------------------------- - .def __indcall - .assume adl=1 - -__indcall equ 00015Ch +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Indirect Call
+; Input:
+; Operand1:
+; iy : 24 bit
+;
+; Output:
+; Registers Used:
+;-------------------------------------------------------------------------
+ .def __indcall
+ .assume adl=1
+
+__indcall equ 00015Ch
diff --git a/frontends/calculator/CEdev/lib/shared/ineg.src b/frontends/calculator/CEdev/lib/shared/ineg.src index 4bb0b46..3444991 100644 --- a/frontends/calculator/CEdev/lib/shared/ineg.src +++ b/frontends/calculator/CEdev/lib/shared/ineg.src @@ -1,16 +1,16 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer/short NEG. -; Input: -; Operand1: -; hl : 24/16 bit -; -; Output: -; Result: hl : 24/16 bit ( 0 - hl) -; Registers Used: -; a,de -;------------------------------------------------------------------------- - .def __ineg - .assume adl=1 - -__ineg equ 000160h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer/short NEG.
+; Input:
+; Operand1:
+; hl : 24/16 bit
+;
+; Output:
+; Result: hl : 24/16 bit ( 0 - hl)
+; Registers Used:
+; a,de
+;-------------------------------------------------------------------------
+ .def __ineg
+ .assume adl=1
+
+__ineg equ 000160h
diff --git a/frontends/calculator/CEdev/lib/shared/inot.src b/frontends/calculator/CEdev/lib/shared/inot.src index 8fcf888..74efd5b 100644 --- a/frontends/calculator/CEdev/lib/shared/inot.src +++ b/frontends/calculator/CEdev/lib/shared/inot.src @@ -1,15 +1,15 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer/Short NOT. -; Input: -; Operand1: -; hl : 24/16 bit -; -; Output: -; Result: hl : 24/16 bit -; Registers Used: -;------------------------------------------------------------------------- - .def __inot - .assume adl=1 - -__inot equ 000164h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer/Short NOT.
+; Input:
+; Operand1:
+; hl : 24/16 bit
+;
+; Output:
+; Result: hl : 24/16 bit
+; Registers Used:
+;-------------------------------------------------------------------------
+ .def __inot
+ .assume adl=1
+
+__inot equ 000164h
diff --git a/frontends/calculator/CEdev/lib/shared/interrupts.src b/frontends/calculator/CEdev/lib/shared/interrupts.src index 64d30d5..868906b 100644 --- a/frontends/calculator/CEdev/lib/shared/interrupts.src +++ b/frontends/calculator/CEdev/lib/shared/interrupts.src @@ -1,142 +1,142 @@ - .def _int_Initialize - .def _int_Handler - .def _int_SetVector - .def _int_Reset - .assume adl=1 - -;------------------------------------------------------------------------------- -; Interrupts equates -mpIntStatus equ 0F00000h -mpIntMask equ 0F00004h -mpIntAck equ 0F00008h -mpIntLachEnable equ 0F0000Ch -mpIntXor equ 0F00010h -mpIntStatusMasked equ 0F00014h - -intOnKey equ 1 -intTimer1 equ 2 -intTimer2 equ 4 -intTimer3 equ 8 -intOsTimer equ 10h -intKbd equ 400h -intLcd equ 800h -intRtc equ 1000h - -;------------------------------------------------------------------------------- -_int_Initialize: - di - ld de,lconf - ld hl,mpIntMask - ld bc,16 - ldir - ld hl,cconf - ld de,mpIntMask - ld bc,16 - ldir - ld hl,0D18879h - ld de,0C90611h - ld (hl),de - dec hl - ld (hl),0EDh - push hl - inc d - call 0D18878h - ld hl, 0E10010h | ((_int_Handler >> 8) & 000FF00h) - ld de, 0C3h | ((_int_Handler << 8) & 0FFFF00h) - ld (hl),h - inc hl - ld (hl),de - ld hl,0E30800h - ld bc,0401h - ld a,0E1h - call 00210E0h ; _Memset - ld hl,0E308h - ld i,hl - im 2 - ld d,3 - ret - -_int_Handler: - ex af,af' - exx - ld hl,(mpIntStatusMasked) - add hl,hl - inc hl - add hl,hl - xor a,a -isr_loop: - inc a - add hl,hl - jr nc,isr_loop -identified: - dec a - add a,a - add a,a - ld (isr_dispatch_smc+1),a - exx - ex af, af' -isr_dispatch_smc: - jr $+2 -iv_list: - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt - jp unhandledInt -unhandledInt: - ei - ret - -;------------------------------------------------------------------------------- -_int_SetVector: - ld iy,0 - add iy,sp - ld a,21 - ld l,(iy+3) - sub a,l - ld l,a - ld h,4 - mlt hl - ld de,iv_list+1 - add hl,de - ld de,(iy+6) - ld (hl),de - ret - -;------------------------------------------------------------------------------- -_int_Reset: - di - ld hl, lconf - ld de, mpIntMask - ld bc, 16 - ldir - im 1 - ret - segment bss -lconf: ds 16 - segment data -cconf: ; Mask - db 000h,000h,000h,000h - ; ACK - db 0FFh,0FFh,0FFh,0FFh - ; Latch - db 000h,000h,000h,000h - ; Invert - db 000h,000h,000h,000h + .def _int_Initialize
+ .def _int_Handler
+ .def _int_SetVector
+ .def _int_Reset
+ .assume adl=1
+
+;-------------------------------------------------------------------------------
+; Interrupts equates
+mpIntStatus equ 0F00000h
+mpIntMask equ 0F00004h
+mpIntAck equ 0F00008h
+mpIntLachEnable equ 0F0000Ch
+mpIntXor equ 0F00010h
+mpIntStatusMasked equ 0F00014h
+
+intOnKey equ 1
+intTimer1 equ 2
+intTimer2 equ 4
+intTimer3 equ 8
+intOsTimer equ 10h
+intKbd equ 400h
+intLcd equ 800h
+intRtc equ 1000h
+
+;-------------------------------------------------------------------------------
+_int_Initialize:
+ di
+ ld de,lconf
+ ld hl,mpIntMask
+ ld bc,16
+ ldir
+ ld hl,cconf
+ ld de,mpIntMask
+ ld bc,16
+ ldir
+ ld hl,0D18879h
+ ld de,0C90611h
+ ld (hl),de
+ dec hl
+ ld (hl),0EDh
+ push hl
+ inc d
+ call 0D18878h
+ ld hl, 0E10010h | ((_int_Handler >> 8) & 000FF00h)
+ ld de, 0C3h | ((_int_Handler << 8) & 0FFFF00h)
+ ld (hl),h
+ inc hl
+ ld (hl),de
+ ld hl,0E30800h
+ ld bc,0401h
+ ld a,0E1h
+ call 00210E0h ; _Memset
+ ld hl,0E308h
+ ld i,hl
+ im 2
+ ld d,3
+ ret
+
+_int_Handler:
+ ex af,af'
+ exx
+ ld hl,(mpIntStatusMasked)
+ add hl,hl
+ inc hl
+ add hl,hl
+ xor a,a
+isr_loop:
+ inc a
+ add hl,hl
+ jr nc,isr_loop
+identified:
+ dec a
+ add a,a
+ add a,a
+ ld (isr_dispatch_smc+1),a
+ exx
+ ex af, af'
+isr_dispatch_smc:
+ jr $+2
+iv_list:
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+ jp unhandledInt
+unhandledInt:
+ ei
+ ret
+
+;-------------------------------------------------------------------------------
+_int_SetVector:
+ ld iy,0
+ add iy,sp
+ ld a,21
+ ld l,(iy+3)
+ sub a,l
+ ld l,a
+ ld h,4
+ mlt hl
+ ld de,iv_list+1
+ add hl,de
+ ld de,(iy+6)
+ ld (hl),de
+ ret
+
+;-------------------------------------------------------------------------------
+_int_Reset:
+ di
+ ld hl, lconf
+ ld de, mpIntMask
+ ld bc, 16
+ ldir
+ im 1
+ ret
+ segment bss
+lconf: ds 16
+ segment data
+cconf: ; Mask
+ db 000h,000h,000h,000h
+ ; ACK
+ db 0FFh,0FFh,0FFh,0FFh
+ ; Latch
+ db 000h,000h,000h,000h
+ ; Invert
+ db 000h,000h,000h,000h
diff --git a/frontends/calculator/CEdev/lib/shared/ior.src b/frontends/calculator/CEdev/lib/shared/ior.src index 0edcd5a..c59a38c 100644 --- a/frontends/calculator/CEdev/lib/shared/ior.src +++ b/frontends/calculator/CEdev/lib/shared/ior.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer OR. -; Input: -; Operand1: -; HL : 24 bit -; -; Operand2: -; BC : 24 bit -; -; Output: -; Result: HL : 24 bit -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __ior - .assume adl=1 - -__ior equ 000168h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer OR.
+; Input:
+; Operand1:
+; HL : 24 bit
+;
+; Operand2:
+; BC : 24 bit
+;
+; Output:
+; Result: HL : 24 bit
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __ior
+ .assume adl=1
+
+__ior equ 000168h
diff --git a/frontends/calculator/CEdev/lib/shared/irems.src b/frontends/calculator/CEdev/lib/shared/irems.src index ef4c8d7..b73666e 100644 --- a/frontends/calculator/CEdev/lib/shared/irems.src +++ b/frontends/calculator/CEdev/lib/shared/irems.src @@ -1,19 +1,19 @@ -; (c) Copyright 1999-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer Modulus Signed. -; Input: -; Operand1: -; HL : 24 bits (dividend) -; -; Operand2: -; BC : 24 bits (divisor) -; -; Output: -; Result: HL : 24 bit -; Registers Used: -; de,af -;------------------------------------------------------------------------- - .def __irems - .assume adl=1 - -__irems equ 00016Ch +; (c) Copyright 1999-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer Modulus Signed.
+; Input:
+; Operand1:
+; HL : 24 bits (dividend)
+;
+; Operand2:
+; BC : 24 bits (divisor)
+;
+; Output:
+; Result: HL : 24 bit
+; Registers Used:
+; de,af
+;-------------------------------------------------------------------------
+ .def __irems
+ .assume adl=1
+
+__irems equ 00016Ch
diff --git a/frontends/calculator/CEdev/lib/shared/iremu.src b/frontends/calculator/CEdev/lib/shared/iremu.src index dac22a0..e519264 100644 --- a/frontends/calculator/CEdev/lib/shared/iremu.src +++ b/frontends/calculator/CEdev/lib/shared/iremu.src @@ -1,21 +1,21 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Unsigned Integer Modulus -; Input: -; Operand1: -; uHL : 24 bits (dividend x) -; -; Operand2: -; uBC : 24 bits (divisor y) -; -; Output: -; Result: uHL : 24 bits (remainder) -; -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __iremu - .assume adl=1 - -__iremu equ 000170h - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Unsigned Integer Modulus
+; Input:
+; Operand1:
+; uHL : 24 bits (dividend x)
+;
+; Operand2:
+; uBC : 24 bits (divisor y)
+;
+; Output:
+; Result: uHL : 24 bits (remainder)
+;
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __iremu
+ .assume adl=1
+
+__iremu equ 000170h
+
diff --git a/frontends/calculator/CEdev/lib/shared/isalnum.src b/frontends/calculator/CEdev/lib/shared/isalnum.src index 12c28a1..7c38350 100644 --- a/frontends/calculator/CEdev/lib/shared/isalnum.src +++ b/frontends/calculator/CEdev/lib/shared/isalnum.src @@ -1,28 +1,28 @@ - .def _isalnum - .ref ___maptab - .assume adl=1 - -; original source -; int isalnum(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(UC|LC|DIG)); -; } - -_isalnum: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,13 - sbc hl,hl - ld l,a - ret + .def _isalnum
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int isalnum(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(UC|LC|DIG));
+; }
+
+_isalnum:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,13
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/isalpha.src b/frontends/calculator/CEdev/lib/shared/isalpha.src index 94627ba..56bfc47 100644 --- a/frontends/calculator/CEdev/lib/shared/isalpha.src +++ b/frontends/calculator/CEdev/lib/shared/isalpha.src @@ -1,27 +1,27 @@ - .def _isalpha - .ref ___maptab - .assume adl=1 - -; original source -; int isalnum(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(UC|LC)); - -_isalpha: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,12 - sbc hl,hl - ld l,a - ret + .def _isalpha
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int isalnum(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(UC|LC));
+
+_isalpha:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,12
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/isascii.src b/frontends/calculator/CEdev/lib/shared/isascii.src index 0c88ffb..2d5b87e 100644 --- a/frontends/calculator/CEdev/lib/shared/isascii.src +++ b/frontends/calculator/CEdev/lib/shared/isascii.src @@ -1,19 +1,19 @@ - .def _isascii - .assume adl=1 - -; original source -; int isascii(int c) { -; return c >= 0 && c < 128; -; } - -_isascii: - pop de - pop hl - push hl - push de - - ld de,-128 - add hl,de - sbc hl,hl - inc hl - ret + .def _isascii
+ .assume adl=1
+
+; original source
+; int isascii(int c) {
+; return c >= 0 && c < 128;
+; }
+
+_isascii:
+ pop de
+ pop hl
+ push hl
+ push de
+
+ ld de,-128
+ add hl,de
+ sbc hl,hl
+ inc hl
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/iscntrl.src b/frontends/calculator/CEdev/lib/shared/iscntrl.src index a8e7864..d6205c7 100644 --- a/frontends/calculator/CEdev/lib/shared/iscntrl.src +++ b/frontends/calculator/CEdev/lib/shared/iscntrl.src @@ -1,27 +1,27 @@ - .def _iscntrl - .ref ___maptab - .assume adl=1 - -;int iscntrl(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(CTL)); -;} - -_iscntrl: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,128 - sbc hl,hl - ld l,a - ret + .def _iscntrl
+ .ref ___maptab
+ .assume adl=1
+
+;int iscntrl(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(CTL));
+;}
+
+_iscntrl:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,128
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/isdigit.src b/frontends/calculator/CEdev/lib/shared/isdigit.src index bbd555a..8517967 100644 --- a/frontends/calculator/CEdev/lib/shared/isdigit.src +++ b/frontends/calculator/CEdev/lib/shared/isdigit.src @@ -1,27 +1,27 @@ - .def _isdigit - .ref ___maptab - .assume adl=1 - -;int isdigit(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(DIG)); -;} - -_isdigit: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,1 - sbc hl,hl - ld l,a - ret + .def _isdigit
+ .ref ___maptab
+ .assume adl=1
+
+;int isdigit(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(DIG));
+;}
+
+_isdigit:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,1
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/isgraph.src b/frontends/calculator/CEdev/lib/shared/isgraph.src index 59bc61e..063009d 100644 --- a/frontends/calculator/CEdev/lib/shared/isgraph.src +++ b/frontends/calculator/CEdev/lib/shared/isgraph.src @@ -1,28 +1,28 @@ - .def _isgraph - .ref ___maptab - .assume adl=1 - -; original source -; int isgraph(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(UC|LC|DIG|PUN)); -; } - -_isgraph: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,15 - sbc hl,hl - ld l,a - ret + .def _isgraph
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int isgraph(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(UC|LC|DIG|PUN));
+; }
+
+_isgraph:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,15
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/ishl.src b/frontends/calculator/CEdev/lib/shared/ishl.src index b9a7347..084ea40 100644 --- a/frontends/calculator/CEdev/lib/shared/ishl.src +++ b/frontends/calculator/CEdev/lib/shared/ishl.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer Shift Left -; Input: -; Operand1: -; BC : 24 bit number of bits to shift -; Asuume B=0 C=shift count -; Operand2: -; HL : 24 bit value to be shifted by C -; -; Output: -; Result: HL : 24 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __ishl, __ishl_b - .assume adl=1 - -__ishl_b equ 000178h -__ishl equ 000174h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer Shift Left
+; Input:
+; Operand1:
+; BC : 24 bit number of bits to shift
+; Asuume B=0 C=shift count
+; Operand2:
+; HL : 24 bit value to be shifted by C
+;
+; Output:
+; Result: HL : 24 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __ishl, __ishl_b
+ .assume adl=1
+
+__ishl_b equ 000178h
+__ishl equ 000174h
diff --git a/frontends/calculator/CEdev/lib/shared/ishrs.src b/frontends/calculator/CEdev/lib/shared/ishrs.src index 79125e7..0c0a3c7 100644 --- a/frontends/calculator/CEdev/lib/shared/ishrs.src +++ b/frontends/calculator/CEdev/lib/shared/ishrs.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer Shift Right Signed -; Input: -; Operand1: -; BC : 24 bit number of bits to shift -; Assume B=0 C=shift count -; Operand2: -; HL : 24 bit value to be shifted by C -; -; Output: -; Result: HL : 24 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __ishrs, __ishrs_b - .assume adl=1 - -__ishrs_b equ 000180h -__ishrs equ 00017Ch +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer Shift Right Signed
+; Input:
+; Operand1:
+; BC : 24 bit number of bits to shift
+; Assume B=0 C=shift count
+; Operand2:
+; HL : 24 bit value to be shifted by C
+;
+; Output:
+; Result: HL : 24 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __ishrs, __ishrs_b
+ .assume adl=1
+
+__ishrs_b equ 000180h
+__ishrs equ 00017Ch
diff --git a/frontends/calculator/CEdev/lib/shared/ishru.src b/frontends/calculator/CEdev/lib/shared/ishru.src index ed190d4..f369fa9 100644 --- a/frontends/calculator/CEdev/lib/shared/ishru.src +++ b/frontends/calculator/CEdev/lib/shared/ishru.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer Shift Right Unsigned -; Input: -; Operand1: -; BC : 24 bit number of bits to shift -; Assume B=0 C=shift count -; Operand2: -; HL : 24 bit value to be shifted by C -; -; Output: -; Result: HL : 24 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __ishru, __ishru_b - .assume adl=1 - -__ishru_b equ 000188h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer Shift Right Unsigned
+; Input:
+; Operand1:
+; BC : 24 bit number of bits to shift
+; Assume B=0 C=shift count
+; Operand2:
+; HL : 24 bit value to be shifted by C
+;
+; Output:
+; Result: HL : 24 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __ishru, __ishru_b
+ .assume adl=1
+
+__ishru_b equ 000188h
__ishru equ 000184h
\ No newline at end of file diff --git a/frontends/calculator/CEdev/lib/shared/isinf.src b/frontends/calculator/CEdev/lib/shared/isinf.src index 1c0c46b..f3782a9 100644 --- a/frontends/calculator/CEdev/lib/shared/isinf.src +++ b/frontends/calculator/CEdev/lib/shared/isinf.src @@ -1,20 +1,20 @@ - .ref __frameset0 - .def _isinf - .assume adl=1 - -; int isinf(double n); - -_isinf: - call __frameset0 - ld hl,(ix+6) - adc hl,hl - jr nz,l_1 - ld hl,(ix+8) - add hl,hl - inc h -l_1: ld hl,0 - jr nz,l_2 - inc hl -l_2: ld sp,ix - pop ix - ret + .ref __frameset0
+ .def _isinf
+ .assume adl=1
+
+; int isinf(double n);
+
+_isinf:
+ call __frameset0
+ ld hl,(ix+6)
+ adc hl,hl
+ jr nz,l_1
+ ld hl,(ix+8)
+ add hl,hl
+ inc h
+l_1: ld hl,0
+ jr nz,l_2
+ inc hl
+l_2: ld sp,ix
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/islower.src b/frontends/calculator/CEdev/lib/shared/islower.src index 3f72f9c..260a1d0 100644 --- a/frontends/calculator/CEdev/lib/shared/islower.src +++ b/frontends/calculator/CEdev/lib/shared/islower.src @@ -1,29 +1,29 @@ - .def _islower - .ref ___maptab - .assume adl=1 - -; original source -; int islower(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(LC)); -; } - -_islower: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - ld a,e - and a,128 - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,4 - sbc hl,hl - ld l,a - ret + .def _islower
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int islower(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(LC));
+; }
+
+_islower:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ ld a,e
+ and a,128
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,4
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/isnan.src b/frontends/calculator/CEdev/lib/shared/isnan.src index 129bf69..d3e2b44 100644 --- a/frontends/calculator/CEdev/lib/shared/isnan.src +++ b/frontends/calculator/CEdev/lib/shared/isnan.src @@ -1,20 +1,20 @@ - .ref __frameset0 - .def _isnan - .assume adl=1 - -; int isnan(double n); - -_isnan: - call __frameset0 - ld hl,(ix+6) - adc hl,hl - jr z,l_1 - ld hl,(ix+8) - add hl,hl -l_1: inc h - ld hl,0 - jr nz,l_2 - inc hl -l_2: ld sp,ix - pop ix - ret + .ref __frameset0
+ .def _isnan
+ .assume adl=1
+
+; int isnan(double n);
+
+_isnan:
+ call __frameset0
+ ld hl,(ix+6)
+ adc hl,hl
+ jr z,l_1
+ ld hl,(ix+8)
+ add hl,hl
+l_1: inc h
+ ld hl,0
+ jr nz,l_2
+ inc hl
+l_2: ld sp,ix
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/isprint.src b/frontends/calculator/CEdev/lib/shared/isprint.src index 79b7bbf..ed19c41 100644 --- a/frontends/calculator/CEdev/lib/shared/isprint.src +++ b/frontends/calculator/CEdev/lib/shared/isprint.src @@ -1,28 +1,28 @@ - .def _isprint - .ref ___maptab - .assume adl=1 - -; original source -; int isprint(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(UC|LC|DIG|PUN|SP)); -; } - -_isprint: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,47 - sbc hl,hl - ld l,a - ret + .def _isprint
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int isprint(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(UC|LC|DIG|PUN|SP));
+; }
+
+_isprint:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,47
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/ispunct.src b/frontends/calculator/CEdev/lib/shared/ispunct.src index 52a2e79..baefad2 100644 --- a/frontends/calculator/CEdev/lib/shared/ispunct.src +++ b/frontends/calculator/CEdev/lib/shared/ispunct.src @@ -1,28 +1,28 @@ - .def _ispunct - .ref ___maptab - .assume adl=1 - -; original source -; int ispunct(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(PUN)); -; } - -_ispunct: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,2 - sbc hl,hl - ld l,a - ret + .def _ispunct
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int ispunct(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(PUN));
+; }
+
+_ispunct:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,2
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/isspace.src b/frontends/calculator/CEdev/lib/shared/isspace.src index 4e670f2..e6b8ec6 100644 --- a/frontends/calculator/CEdev/lib/shared/isspace.src +++ b/frontends/calculator/CEdev/lib/shared/isspace.src @@ -1,28 +1,28 @@ - .def _isspace - .ref ___maptab - .assume adl=1 - -; original source -; int isspace(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(WS)); -; } - -_isspace: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,64 - sbc hl,hl - ld l,a - ret + .def _isspace
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int isspace(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(WS));
+; }
+
+_isspace:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,64
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/istix.src b/frontends/calculator/CEdev/lib/shared/istix.src index 8570366..6e986e1 100644 --- a/frontends/calculator/CEdev/lib/shared/istix.src +++ b/frontends/calculator/CEdev/lib/shared/istix.src @@ -1,18 +1,18 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer store (ix+nnnnnn),HL -; Input: -; Operand1: -; BC : 24-bit offset from ix -; HL : 24-bit integer to store -; -; Output: -; -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __istix - .assume adl=1 - -__istix equ 00018Ch +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer store (ix+nnnnnn),HL
+; Input:
+; Operand1:
+; BC : 24-bit offset from ix
+; HL : 24-bit integer to store
+;
+; Output:
+;
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __istix
+ .assume adl=1
+
+__istix equ 00018Ch
diff --git a/frontends/calculator/CEdev/lib/shared/istiy.src b/frontends/calculator/CEdev/lib/shared/istiy.src index 7ca71ea..d336856 100644 --- a/frontends/calculator/CEdev/lib/shared/istiy.src +++ b/frontends/calculator/CEdev/lib/shared/istiy.src @@ -1,18 +1,18 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer store (iy+nnnnnn),HL -; Input: -; Operand1: -; BC : 24-bit offset from iy -; HL : 24-bit integer to store -; -; Output: -; -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __istiy - .assume adl=1 - -__istiy equ 000190h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer store (iy+nnnnnn),HL
+; Input:
+; Operand1:
+; BC : 24-bit offset from iy
+; HL : 24-bit integer to store
+;
+; Output:
+;
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __istiy
+ .assume adl=1
+
+__istiy equ 000190h
diff --git a/frontends/calculator/CEdev/lib/shared/isupper.src b/frontends/calculator/CEdev/lib/shared/isupper.src index 300474e..79b812e 100644 --- a/frontends/calculator/CEdev/lib/shared/isupper.src +++ b/frontends/calculator/CEdev/lib/shared/isupper.src @@ -1,28 +1,28 @@ - .def _isupper - .ref ___maptab - .assume adl=1 - -; original source -; int isupper(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(UC)); -; } - -_isupper: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,8 - sbc hl,hl - ld l,a - ret + .def _isupper
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int isupper(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(UC));
+; }
+
+_isupper:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,8
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/isxdigit.src b/frontends/calculator/CEdev/lib/shared/isxdigit.src index 9db54a4..354a161 100644 --- a/frontends/calculator/CEdev/lib/shared/isxdigit.src +++ b/frontends/calculator/CEdev/lib/shared/isxdigit.src @@ -1,28 +1,28 @@ - .def _isxdigit - .ref ___maptab - .assume adl=1 - -; original source -; int isxdigit(int c) { -; if( (unsigned char)c & (unsigned char)0x80 ) -; return (0); -; return(__maptab[c] & (unsigned char)(DIG|HEX)); -; } - -_isxdigit: - pop hl - pop de - push de - push hl - or a,a - sbc hl,hl - bit 7,e - ret nz - ex de,hl - ld de,___maptab - add hl,de - ld a,(hl) - and a,17 - sbc hl,hl - ld l,a - ret + .def _isxdigit
+ .ref ___maptab
+ .assume adl=1
+
+; original source
+; int isxdigit(int c) {
+; if( (unsigned char)c & (unsigned char)0x80 )
+; return (0);
+; return(__maptab[c] & (unsigned char)(DIG|HEX));
+; }
+
+_isxdigit:
+ pop hl
+ pop de
+ push de
+ push hl
+ or a,a
+ sbc hl,hl
+ bit 7,e
+ ret nz
+ ex de,hl
+ ld de,___maptab
+ add hl,de
+ ld a,(hl)
+ and a,17
+ sbc hl,hl
+ ld l,a
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/itol.src b/frontends/calculator/CEdev/lib/shared/itol.src index 8efd34d..81e7315 100644 --- a/frontends/calculator/CEdev/lib/shared/itol.src +++ b/frontends/calculator/CEdev/lib/shared/itol.src @@ -1,16 +1,16 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Signed Integer to Long conversion -; Input: -; Operand1: -; BC : 24 bit -; -; Output: -; Result: A:BC : 32 bit -; Registers Used: -; -;------------------------------------------------------------------------- - .def __itol - .assume adl=1 - -__itol equ 000194h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Signed Integer to Long conversion
+; Input:
+; Operand1:
+; BC : 24 bit
+;
+; Output:
+; Result: A:BC : 32 bit
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __itol
+ .assume adl=1
+
+__itol equ 000194h
diff --git a/frontends/calculator/CEdev/lib/shared/ixor.src b/frontends/calculator/CEdev/lib/shared/ixor.src index 75299dd..7b6b41b 100644 --- a/frontends/calculator/CEdev/lib/shared/ixor.src +++ b/frontends/calculator/CEdev/lib/shared/ixor.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer XOR. -; Input: -; Operand1: -; hl : 24 bit -; -; Operand2: -; bc : 24 bit -; -; Output: -; Result: hl : 24 bit -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __ixor - .assume adl=1 - -__ixor equ 000198h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer XOR.
+; Input:
+; Operand1:
+; hl : 24 bit
+;
+; Operand2:
+; bc : 24 bit
+;
+; Output:
+; Result: hl : 24 bit
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __ixor
+ .assume adl=1
+
+__ixor equ 000198h
diff --git a/frontends/calculator/CEdev/lib/shared/labs.src b/frontends/calculator/CEdev/lib/shared/labs.src index 38cd6dc..dfe7f98 100644 --- a/frontends/calculator/CEdev/lib/shared/labs.src +++ b/frontends/calculator/CEdev/lib/shared/labs.src @@ -1,24 +1,24 @@ - .ref __frameset0 - .ref __lcmpzero - .ref __setflag - .ref __lneg - .def _labs - .assume adl=1 - -; long labs(long j); - -_labs: - call __frameset0 - ld hl,(ix+6) - ld e,(ix+9) - push hl - push de - call __lcmpzero - call __setflag - pop de - pop hl - jp p,l_1 - call __lneg -l_1: ld sp,ix - pop ix - ret + .ref __frameset0
+ .ref __lcmpzero
+ .ref __setflag
+ .ref __lneg
+ .def _labs
+ .assume adl=1
+
+; long labs(long j);
+
+_labs:
+ call __frameset0
+ ld hl,(ix+6)
+ ld e,(ix+9)
+ push hl
+ push de
+ call __lcmpzero
+ call __setflag
+ pop de
+ pop hl
+ jp p,l_1
+ call __lneg
+l_1: ld sp,ix
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/ladd.src b/frontends/calculator/CEdev/lib/shared/ladd.src index c678a1e..39b16e9 100644 --- a/frontends/calculator/CEdev/lib/shared/ladd.src +++ b/frontends/calculator/CEdev/lib/shared/ladd.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long ADD. -; Input: -; Operand1: -; ehl : 32 bit -; -; Operand2: -; abc : 32 bit -; -; Output: -; Result: ehl : 32 bit -; Registers Used: - -;------------------------------------------------------------------------- - .def __ladd, __ladd_b - .assume adl=1 - -__ladd_b equ 0001A0h -__ladd equ 00019Ch +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long ADD.
+; Input:
+; Operand1:
+; ehl : 32 bit
+;
+; Operand2:
+; abc : 32 bit
+;
+; Output:
+; Result: ehl : 32 bit
+; Registers Used:
+
+;-------------------------------------------------------------------------
+ .def __ladd, __ladd_b
+ .assume adl=1
+
+__ladd_b equ 0001A0h
+__ladd equ 00019Ch
diff --git a/frontends/calculator/CEdev/lib/shared/land.src b/frontends/calculator/CEdev/lib/shared/land.src index 6db554a..ae0460c 100644 --- a/frontends/calculator/CEdev/lib/shared/land.src +++ b/frontends/calculator/CEdev/lib/shared/land.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long AND. -; Input: -; Operand1: -; ehl : 32 bit -; -; Operand2: -; abc : 32 bit -; -; Output: -; Result: ehl : 32 bit -; Registers Used: - -;------------------------------------------------------------------------- - .def __land - .assume adl=1 - -__land equ 0001A4h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long AND.
+; Input:
+; Operand1:
+; ehl : 32 bit
+;
+; Operand2:
+; abc : 32 bit
+;
+; Output:
+; Result: ehl : 32 bit
+; Registers Used:
+
+;-------------------------------------------------------------------------
+ .def __land
+ .assume adl=1
+
+__land equ 0001A4h
diff --git a/frontends/calculator/CEdev/lib/shared/lcmps.src b/frontends/calculator/CEdev/lib/shared/lcmps.src index 495cadd..aaf3163 100644 --- a/frontends/calculator/CEdev/lib/shared/lcmps.src +++ b/frontends/calculator/CEdev/lib/shared/lcmps.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Comparison -; Input: -; Operand1: -; EHL : 32 bits -; -; Operand2: -; ABC : 32 bits -; -; Output: -; Result: F : S,V flags from EHL - ABC -; Registers Used: -; None -;------------------------------------------------------------------------- - .def __lcmps - .assume adl=1 - -__lcmps equ 0001A8h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Comparison
+; Input:
+; Operand1:
+; EHL : 32 bits
+;
+; Operand2:
+; ABC : 32 bits
+;
+; Output:
+; Result: F : S,V flags from EHL - ABC
+; Registers Used:
+; None
+;-------------------------------------------------------------------------
+ .def __lcmps
+ .assume adl=1
+
+__lcmps equ 0001A8h
diff --git a/frontends/calculator/CEdev/lib/shared/lcmpu.src b/frontends/calculator/CEdev/lib/shared/lcmpu.src index 5d7db79..deda9dc 100644 --- a/frontends/calculator/CEdev/lib/shared/lcmpu.src +++ b/frontends/calculator/CEdev/lib/shared/lcmpu.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Unsigned Comparison -; Input: -; Operand1: -; EHL : 32 bits -; -; Operand2: -; ABC : 32 bits -; -; Output: -; Result: F : S,V flags from EHL - ABC -; Registers Used: -; None -;------------------------------------------------------------------------- - .def __lcmpu - .assume adl=1 - -__lcmpu equ 0001ACh +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Unsigned Comparison
+; Input:
+; Operand1:
+; EHL : 32 bits
+;
+; Operand2:
+; ABC : 32 bits
+;
+; Output:
+; Result: F : S,V flags from EHL - ABC
+; Registers Used:
+; None
+;-------------------------------------------------------------------------
+ .def __lcmpu
+ .assume adl=1
+
+__lcmpu equ 0001ACh
diff --git a/frontends/calculator/CEdev/lib/shared/lcmpzero.src b/frontends/calculator/CEdev/lib/shared/lcmpzero.src index 518c58a..e9c19f3 100644 --- a/frontends/calculator/CEdev/lib/shared/lcmpzero.src +++ b/frontends/calculator/CEdev/lib/shared/lcmpzero.src @@ -1,16 +1,16 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Set flag for comparison of 32-bit scalar with constant value zero -; Input: -; Operand1: E:HL register -; -; Output: -; Result: f register -; -; Registers Used: -; None -;------------------------------------------------------------------------- - .def __lcmpzero - .assume adl=1 - -__lcmpzero equ 0001B0h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Set flag for comparison of 32-bit scalar with constant value zero
+; Input:
+; Operand1: E:HL register
+;
+; Output:
+; Result: f register
+;
+; Registers Used:
+; None
+;-------------------------------------------------------------------------
+ .def __lcmpzero
+ .assume adl=1
+
+__lcmpzero equ 0001B0h
diff --git a/frontends/calculator/CEdev/lib/shared/ldiv.src b/frontends/calculator/CEdev/lib/shared/ldiv.src index 8da316b..7f41e0c 100644 --- a/frontends/calculator/CEdev/lib/shared/ldiv.src +++ b/frontends/calculator/CEdev/lib/shared/ldiv.src @@ -1,79 +1,79 @@ -; Copyright (C) 1999-2008 Zilog, Inc, All Rights Reserved -;------------------------------------------------------------------------- -; ldiv function -; -; ldiv_t ldiv(long numer, long denom); -; -;------------------------------------------------------------------------- - .def _ldiv - .ref __ldivs - .ref __lrems - .assume adl=1 - -_ldiv: - - push bc - push af - push de - push hl - - ld hl,27 - add hl,sp - ld a,(hl) - dec hl - dec hl - dec hl - ld bc,(hl) ; aBC : denominator - dec hl - dec hl - dec hl - ld e,(hl) - dec hl - dec hl - dec hl - ld hl,(hl) ; eHL: Numerator - call __ldivs - push de - push hl ; eHL : quotient - - ld hl,27 - add hl,sp - ld e,(hl) - dec hl - dec hl - dec hl - ld hl,(hl) - call __lrems - ld a,e - ex de,hl ;aDE :remainder - - ld hl,21 - add hl,sp - ld hl,(hl) - push hl - - ld bc, 7 - add hl, bc - ld (hl),a - dec hl - dec hl - dec hl - ld (hl),de ; aDE : remainder - - pop hl - pop bc - ld (hl),bc ; bc : 3 LSB of quotient - pop bc - push hl - inc hl - inc hl - inc hl - ld (hl),c ; c : MSB of quotient - pop hl - - pop de - pop de - pop af - pop bc - - ret +; Copyright (C) 1999-2008 Zilog, Inc, All Rights Reserved
+;-------------------------------------------------------------------------
+; ldiv function
+;
+; ldiv_t ldiv(long numer, long denom);
+;
+;-------------------------------------------------------------------------
+ .def _ldiv
+ .ref __ldivs
+ .ref __lrems
+ .assume adl=1
+
+_ldiv:
+
+ push bc
+ push af
+ push de
+ push hl
+
+ ld hl,27
+ add hl,sp
+ ld a,(hl)
+ dec hl
+ dec hl
+ dec hl
+ ld bc,(hl) ; aBC : denominator
+ dec hl
+ dec hl
+ dec hl
+ ld e,(hl)
+ dec hl
+ dec hl
+ dec hl
+ ld hl,(hl) ; eHL: Numerator
+ call __ldivs
+ push de
+ push hl ; eHL : quotient
+
+ ld hl,27
+ add hl,sp
+ ld e,(hl)
+ dec hl
+ dec hl
+ dec hl
+ ld hl,(hl)
+ call __lrems
+ ld a,e
+ ex de,hl ;aDE :remainder
+
+ ld hl,21
+ add hl,sp
+ ld hl,(hl)
+ push hl
+
+ ld bc, 7
+ add hl, bc
+ ld (hl),a
+ dec hl
+ dec hl
+ dec hl
+ ld (hl),de ; aDE : remainder
+
+ pop hl
+ pop bc
+ ld (hl),bc ; bc : 3 LSB of quotient
+ pop bc
+ push hl
+ inc hl
+ inc hl
+ inc hl
+ ld (hl),c ; c : MSB of quotient
+ pop hl
+
+ pop de
+ pop de
+ pop af
+ pop bc
+
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/ldivs.src b/frontends/calculator/CEdev/lib/shared/ldivs.src index 950209e..bc5779c 100644 --- a/frontends/calculator/CEdev/lib/shared/ldivs.src +++ b/frontends/calculator/CEdev/lib/shared/ldivs.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Division Signed -; Input: -; Operand1: -; eHL : 32 bits -; -; Operand2: -; aBC : 32 bits -; Output: -; Result: eHL : 24 bits -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __ldivs - .assume adl=1 - -__ldivs equ 0001B4h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Division Signed
+; Input:
+; Operand1:
+; eHL : 32 bits
+;
+; Operand2:
+; aBC : 32 bits
+; Output:
+; Result: eHL : 24 bits
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __ldivs
+ .assume adl=1
+
+__ldivs equ 0001B4h
diff --git a/frontends/calculator/CEdev/lib/shared/ldivu.src b/frontends/calculator/CEdev/lib/shared/ldivu.src index c570423..32f7c83 100644 --- a/frontends/calculator/CEdev/lib/shared/ldivu.src +++ b/frontends/calculator/CEdev/lib/shared/ldivu.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Division Unsigned -; Input: -; Operand1: -; EuHL : 32 bits -; -; Operand2: -; AuBC : 32 bits -; Output: -; Result: EuHL : 32 bits -; -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __ldivu, __ldvrmu - .assume adl=1 - -__ldivu equ 0001B8h -__ldvrmu equ 0001BCh +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Division Unsigned
+; Input:
+; Operand1:
+; EuHL : 32 bits
+;
+; Operand2:
+; AuBC : 32 bits
+; Output:
+; Result: EuHL : 32 bits
+;
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __ldivu, __ldvrmu
+ .assume adl=1
+
+__ldivu equ 0001B8h
+__ldvrmu equ 0001BCh
diff --git a/frontends/calculator/CEdev/lib/shared/lldix.src b/frontends/calculator/CEdev/lib/shared/lldix.src index 379c4e7..9697040 100644 --- a/frontends/calculator/CEdev/lib/shared/lldix.src +++ b/frontends/calculator/CEdev/lib/shared/lldix.src @@ -1,17 +1,17 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; long load e:hl,(ix+nnnnnn) -; Input: -; Operand1: -; BC : 24-bit offset from ix -; -; Output: -; Result: E:HL : 32 bit -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __lldix - .assume adl=1 - -__lldix equ 0001C0h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; long load e:hl,(ix+nnnnnn)
+; Input:
+; Operand1:
+; BC : 24-bit offset from ix
+;
+; Output:
+; Result: E:HL : 32 bit
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __lldix
+ .assume adl=1
+
+__lldix equ 0001C0h
diff --git a/frontends/calculator/CEdev/lib/shared/lldiy.src b/frontends/calculator/CEdev/lib/shared/lldiy.src index 8e308fd..8cec260 100644 --- a/frontends/calculator/CEdev/lib/shared/lldiy.src +++ b/frontends/calculator/CEdev/lib/shared/lldiy.src @@ -1,17 +1,17 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; long load e:hl,(iy+nnnnnn) -; Input: -; Operand1: -; BC : 24-bit offset from iy -; -; Output: -; Result: E:HL : 32 bit -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __lldiy - .assume adl=1 - -__lldiy equ 0001C4h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; long load e:hl,(iy+nnnnnn)
+; Input:
+; Operand1:
+; BC : 24-bit offset from iy
+;
+; Output:
+; Result: E:HL : 32 bit
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __lldiy
+ .assume adl=1
+
+__lldiy equ 0001C4h
diff --git a/frontends/calculator/CEdev/lib/shared/lmuls.src b/frontends/calculator/CEdev/lib/shared/lmuls.src index 8f75c0b..3629808 100644 --- a/frontends/calculator/CEdev/lib/shared/lmuls.src +++ b/frontends/calculator/CEdev/lib/shared/lmuls.src @@ -1,19 +1,19 @@ -; (c) Copyright 1999-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Multiplication Signed. -; Input: -; Operand1: -; ABC : 32 bits -; -; Operand2: -; EHL : 32 bits -; -; Output: -; Result: ABC : 32 bit -; Registers Used: -; de,af -;------------------------------------------------------------------------- - .def __lmuls - .assume adl=1 - -__lmuls equ 0001C8h +; (c) Copyright 1999-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Multiplication Signed.
+; Input:
+; Operand1:
+; ABC : 32 bits
+;
+; Operand2:
+; EHL : 32 bits
+;
+; Output:
+; Result: ABC : 32 bit
+; Registers Used:
+; de,af
+;-------------------------------------------------------------------------
+ .def __lmuls
+ .assume adl=1
+
+__lmuls equ 0001C8h
diff --git a/frontends/calculator/CEdev/lib/shared/lmulu.src b/frontends/calculator/CEdev/lib/shared/lmulu.src index f84fe24..87bc9d7 100644 --- a/frontends/calculator/CEdev/lib/shared/lmulu.src +++ b/frontends/calculator/CEdev/lib/shared/lmulu.src @@ -1,22 +1,22 @@ -; (c) Copyright 1999-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Multiplication Signed/Unsigned. -; Note: When multipying two n-bit values, the low-order n-bits -; of the product are the same, whether or not the values -; are considered signed or unsigned. -; Input: -; Operand1: -; EuHL : 32 bits -; -; Operand2: -; AuBC : 32 bits -; -; Output: -; Result: EuHL : 32 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __lmulu - .assume adl=1 - -__lmulu equ 0001CCh +; (c) Copyright 1999-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Multiplication Signed/Unsigned.
+; Note: When multipying two n-bit values, the low-order n-bits
+; of the product are the same, whether or not the values
+; are considered signed or unsigned.
+; Input:
+; Operand1:
+; EuHL : 32 bits
+;
+; Operand2:
+; AuBC : 32 bits
+;
+; Output:
+; Result: EuHL : 32 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __lmulu
+ .assume adl=1
+
+__lmulu equ 0001CCh
diff --git a/frontends/calculator/CEdev/lib/shared/lneg.src b/frontends/calculator/CEdev/lib/shared/lneg.src index 3e8b407..ab44f20 100644 --- a/frontends/calculator/CEdev/lib/shared/lneg.src +++ b/frontends/calculator/CEdev/lib/shared/lneg.src @@ -1,16 +1,16 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long NEG. -; Input: -; Operand1: -; EuHL : 32 bit -; -; Output: -; Result: EuHL : 32 bit -; Registers Used: -; flags -;------------------------------------------------------------------------- - .def __lneg - .assume adl=1 - -__lneg equ 0001D0h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long NEG.
+; Input:
+; Operand1:
+; EuHL : 32 bit
+;
+; Output:
+; Result: EuHL : 32 bit
+; Registers Used:
+; flags
+;-------------------------------------------------------------------------
+ .def __lneg
+ .assume adl=1
+
+__lneg equ 0001D0h
diff --git a/frontends/calculator/CEdev/lib/shared/lnot.src b/frontends/calculator/CEdev/lib/shared/lnot.src index 774b304..083a572 100644 --- a/frontends/calculator/CEdev/lib/shared/lnot.src +++ b/frontends/calculator/CEdev/lib/shared/lnot.src @@ -1,16 +1,16 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long NOT. -; Input: -; Operand1: -; eHL : 32 bit -; -; Output: -; Result: eHL : 32 bit -; Registers Used: -; None -;------------------------------------------------------------------------- - .def __lnot - .assume adl=1 - -__lnot equ 0001D4h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long NOT.
+; Input:
+; Operand1:
+; eHL : 32 bit
+;
+; Output:
+; Result: eHL : 32 bit
+; Registers Used:
+; None
+;-------------------------------------------------------------------------
+ .def __lnot
+ .assume adl=1
+
+__lnot equ 0001D4h
diff --git a/frontends/calculator/CEdev/lib/shared/log2.src b/frontends/calculator/CEdev/lib/shared/log2.src index 5630503..028886f 100644 --- a/frontends/calculator/CEdev/lib/shared/log2.src +++ b/frontends/calculator/CEdev/lib/shared/log2.src @@ -1,27 +1,27 @@ - .def _log2 - .ref _log - .ref __fdiv - .ref __frameset0 - .assume adl=1 - -_log2: - call __frameset0 - ld c,(ix+9) - ld b,0 - push bc - ld bc,(ix+6) - push bc - call _log - push hl - pop bc - ld a,e - ld hl,3240472 - ld e,63 - call __fdiv - ld e,a - push bc - pop hl - ld sp,ix - pop ix - ret - + .def _log2
+ .ref _log
+ .ref __fdiv
+ .ref __frameset0
+ .assume adl=1
+
+_log2:
+ call __frameset0
+ ld c,(ix+9)
+ ld b,0
+ push bc
+ ld bc,(ix+6)
+ push bc
+ call _log
+ push hl
+ pop bc
+ ld a,e
+ ld hl,3240472
+ ld e,63
+ call __fdiv
+ ld e,a
+ push bc
+ pop hl
+ ld sp,ix
+ pop ix
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/longjmp.src b/frontends/calculator/CEdev/lib/shared/longjmp.src index 0399ff0..54baa77 100644 --- a/frontends/calculator/CEdev/lib/shared/longjmp.src +++ b/frontends/calculator/CEdev/lib/shared/longjmp.src @@ -1,4 +1,4 @@ - .def _longjmp - .assume adl=1 - + .def _longjmp
+ .assume adl=1
+
_longjmp equ 000098h
\ No newline at end of file diff --git a/frontends/calculator/CEdev/lib/shared/lor.src b/frontends/calculator/CEdev/lib/shared/lor.src index b9a3c95..91fef65 100644 --- a/frontends/calculator/CEdev/lib/shared/lor.src +++ b/frontends/calculator/CEdev/lib/shared/lor.src @@ -1,19 +1,19 @@ -; (c) Copyright 1999-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long OR. -; Input: -; Operand1: -; ehl : 32 bit -; -; Operand2: -; abc : 32 bit -; -; Output: -; Result: ehl : 32 bit -; Registers Used: -; -;------------------------------------------------------------------------- - .def __lor - .assume adl=1 - -__lor equ 0001D8h +; (c) Copyright 1999-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long OR.
+; Input:
+; Operand1:
+; ehl : 32 bit
+;
+; Operand2:
+; abc : 32 bit
+;
+; Output:
+; Result: ehl : 32 bit
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __lor
+ .assume adl=1
+
+__lor equ 0001D8h
diff --git a/frontends/calculator/CEdev/lib/shared/lrems.src b/frontends/calculator/CEdev/lib/shared/lrems.src index 958404b..8e1d9bc 100644 --- a/frontends/calculator/CEdev/lib/shared/lrems.src +++ b/frontends/calculator/CEdev/lib/shared/lrems.src @@ -1,19 +1,19 @@ -; (c) Copyright 1999-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Modulus Signed. -; Input: -; Operand1: -; EHL : 32 bits (dividend) -; -; Operand2: -; ABC : 32 bits (divisor) -; -; Output: -; Result: EHL : 32 bit -; Registers Used: -; de,af -;------------------------------------------------------------------------- - .def __lrems - .assume adl=1 - -__lrems equ 0001DCh +; (c) Copyright 1999-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Modulus Signed.
+; Input:
+; Operand1:
+; EHL : 32 bits (dividend)
+;
+; Operand2:
+; ABC : 32 bits (divisor)
+;
+; Output:
+; Result: EHL : 32 bit
+; Registers Used:
+; de,af
+;-------------------------------------------------------------------------
+ .def __lrems
+ .assume adl=1
+
+__lrems equ 0001DCh
diff --git a/frontends/calculator/CEdev/lib/shared/lremu.src b/frontends/calculator/CEdev/lib/shared/lremu.src index 6ed28b1..9b00573 100644 --- a/frontends/calculator/CEdev/lib/shared/lremu.src +++ b/frontends/calculator/CEdev/lib/shared/lremu.src @@ -1,19 +1,19 @@ -; (c) Copyright 1999-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Modulus Unsigned. -; Input: -; Operand1: -; EuHL : 32 bits (dividend x) -; -; Operand2: -; AuBC : 32 bits (divisor y) -; -; Output: -; Result: EuHL : 32 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __lremu - .assume adl=1 - -__lremu equ 0001E0h +; (c) Copyright 1999-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Modulus Unsigned.
+; Input:
+; Operand1:
+; EuHL : 32 bits (dividend x)
+;
+; Operand2:
+; AuBC : 32 bits (divisor y)
+;
+; Output:
+; Result: EuHL : 32 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __lremu
+ .assume adl=1
+
+__lremu equ 0001E0h
diff --git a/frontends/calculator/CEdev/lib/shared/lshl.src b/frontends/calculator/CEdev/lib/shared/lshl.src index 3038a0d..c49c3d9 100644 --- a/frontends/calculator/CEdev/lib/shared/lshl.src +++ b/frontends/calculator/CEdev/lib/shared/lshl.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Shift Left -; Input: -; Operand1: -; AuBC : 32 bit value to be shifted -; -; Operand2: -; L : number of bits to shift -; -; Output: -; Result: AuBC : 32 bit result -; Registers Used: -; flags -;------------------------------------------------------------------------- - .def __lshl - .assume adl=1 - -__lshl equ 0001E4h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Shift Left
+; Input:
+; Operand1:
+; AuBC : 32 bit value to be shifted
+;
+; Operand2:
+; L : number of bits to shift
+;
+; Output:
+; Result: AuBC : 32 bit result
+; Registers Used:
+; flags
+;-------------------------------------------------------------------------
+ .def __lshl
+ .assume adl=1
+
+__lshl equ 0001E4h
diff --git a/frontends/calculator/CEdev/lib/shared/lshrs.src b/frontends/calculator/CEdev/lib/shared/lshrs.src index a8a35d1..08bb693 100644 --- a/frontends/calculator/CEdev/lib/shared/lshrs.src +++ b/frontends/calculator/CEdev/lib/shared/lshrs.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Shift Right Signed -; Input: -; Operand1: -; AuBC : 32 bit value to be shifted by L -; -; Operand2: -; L : number of bits to shift -; -; Output: -; Result: AuBC : 32 bit -; Registers Used: -; flags -;------------------------------------------------------------------------- - .def __lshrs - .assume adl=1 - -__lshrs equ 0001E8h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Shift Right Signed
+; Input:
+; Operand1:
+; AuBC : 32 bit value to be shifted by L
+;
+; Operand2:
+; L : number of bits to shift
+;
+; Output:
+; Result: AuBC : 32 bit
+; Registers Used:
+; flags
+;-------------------------------------------------------------------------
+ .def __lshrs
+ .assume adl=1
+
+__lshrs equ 0001E8h
diff --git a/frontends/calculator/CEdev/lib/shared/lshru.src b/frontends/calculator/CEdev/lib/shared/lshru.src index 5334d7f..2734ecf 100644 --- a/frontends/calculator/CEdev/lib/shared/lshru.src +++ b/frontends/calculator/CEdev/lib/shared/lshru.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Shift Right Unsigned -; Input: -; Operand1: -; AuBC : 32 bit value to be shifted by L -; -; Operand2: -; L : number of bits to shift -; -; Output: -; Result: AuBC : 32 bit -; Registers Used: -; flags -;------------------------------------------------------------------------- - .def __lshru - .assume adl=1 - -__lshru equ 0001ECh +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Shift Right Unsigned
+; Input:
+; Operand1:
+; AuBC : 32 bit value to be shifted by L
+;
+; Operand2:
+; L : number of bits to shift
+;
+; Output:
+; Result: AuBC : 32 bit
+; Registers Used:
+; flags
+;-------------------------------------------------------------------------
+ .def __lshru
+ .assume adl=1
+
+__lshru equ 0001ECh
diff --git a/frontends/calculator/CEdev/lib/shared/lstix.src b/frontends/calculator/CEdev/lib/shared/lstix.src index 22c014e..749d3ff 100644 --- a/frontends/calculator/CEdev/lib/shared/lstix.src +++ b/frontends/calculator/CEdev/lib/shared/lstix.src @@ -1,17 +1,17 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; long store (ix+nnnnnn),H:HL -; Input: -; Operand1: -; BC : 24-bit offset from ix -; E:HL : 32-bit value -; -; Output: -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __lstix - .assume adl=1 - -__lstix equ 0001F0h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; long store (ix+nnnnnn),H:HL
+; Input:
+; Operand1:
+; BC : 24-bit offset from ix
+; E:HL : 32-bit value
+;
+; Output:
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __lstix
+ .assume adl=1
+
+__lstix equ 0001F0h
diff --git a/frontends/calculator/CEdev/lib/shared/lstiy.src b/frontends/calculator/CEdev/lib/shared/lstiy.src index e141502..4da53a6 100644 --- a/frontends/calculator/CEdev/lib/shared/lstiy.src +++ b/frontends/calculator/CEdev/lib/shared/lstiy.src @@ -1,17 +1,17 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; long store (iy+nnnnnn),E:HL -; Input: -; Operand1: -; BC : 24-bit offset from iy -; E:HL : 32-bit value -; -; Output: -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __lstiy - .assume adl=1 - -__lstiy equ 0001F4h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; long store (iy+nnnnnn),E:HL
+; Input:
+; Operand1:
+; BC : 24-bit offset from iy
+; E:HL : 32-bit value
+;
+; Output:
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __lstiy
+ .assume adl=1
+
+__lstiy equ 0001F4h
diff --git a/frontends/calculator/CEdev/lib/shared/lsub.src b/frontends/calculator/CEdev/lib/shared/lsub.src index ef51463..1cccbd4 100644 --- a/frontends/calculator/CEdev/lib/shared/lsub.src +++ b/frontends/calculator/CEdev/lib/shared/lsub.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long Subtract Op1 - Op2 -; Input: -; Operand1: -; EHL : 32 bits -; -; Operand2: -; ABC : 32 bits -; -; Output: -; Result: EHL : 32 bits -; Registers Used: -; flags -;------------------------------------------------------------------------- - .def __lsub - .assume adl=1 - -__lsub equ 0001F8h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long Subtract Op1 - Op2
+; Input:
+; Operand1:
+; EHL : 32 bits
+;
+; Operand2:
+; ABC : 32 bits
+;
+; Output:
+; Result: EHL : 32 bits
+; Registers Used:
+; flags
+;-------------------------------------------------------------------------
+ .def __lsub
+ .assume adl=1
+
+__lsub equ 0001F8h
diff --git a/frontends/calculator/CEdev/lib/shared/lxor.src b/frontends/calculator/CEdev/lib/shared/lxor.src index c14d3cc..b8753d1 100644 --- a/frontends/calculator/CEdev/lib/shared/lxor.src +++ b/frontends/calculator/CEdev/lib/shared/lxor.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Long XOR. -; Input: -; Operand1: -; ehl : 32 bit -; -; Operand2: -; abc : 32 bit -; -; Output: -; Result: ehl : 32 bit -; Registers Used: -; -;------------------------------------------------------------------------- - .def __lxor - .assume adl=1 - -__lxor equ 0001FCh +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Long XOR.
+; Input:
+; Operand1:
+; ehl : 32 bit
+;
+; Operand2:
+; abc : 32 bit
+;
+; Output:
+; Result: ehl : 32 bit
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __lxor
+ .assume adl=1
+
+__lxor equ 0001FCh
diff --git a/frontends/calculator/CEdev/lib/shared/memchr.src b/frontends/calculator/CEdev/lib/shared/memchr.src index 1dec0c8..cc1646c 100644 --- a/frontends/calculator/CEdev/lib/shared/memchr.src +++ b/frontends/calculator/CEdev/lib/shared/memchr.src @@ -1,6 +1,6 @@ - .def _memchr - .assume adl=1 - -; void *memchr(const void *buf, int c, size_t count); - -_memchr equ 00009Ch + .def _memchr
+ .assume adl=1
+
+; void *memchr(const void *buf, int c, size_t count);
+
+_memchr equ 00009Ch
diff --git a/frontends/calculator/CEdev/lib/shared/memcmp.src b/frontends/calculator/CEdev/lib/shared/memcmp.src index 4658030..72477a6 100644 --- a/frontends/calculator/CEdev/lib/shared/memcmp.src +++ b/frontends/calculator/CEdev/lib/shared/memcmp.src @@ -1,6 +1,6 @@ - .def _memcmp - .assume adl=1 - -; int memcmp(const void *buf1, const void *buf2, size_t count); - -_memcmp equ 0000A0h + .def _memcmp
+ .assume adl=1
+
+; int memcmp(const void *buf1, const void *buf2, size_t count);
+
+_memcmp equ 0000A0h
diff --git a/frontends/calculator/CEdev/lib/shared/memcpy.src b/frontends/calculator/CEdev/lib/shared/memcpy.src index 9ecc289..3049840 100644 --- a/frontends/calculator/CEdev/lib/shared/memcpy.src +++ b/frontends/calculator/CEdev/lib/shared/memcpy.src @@ -1,6 +1,6 @@ - .def _memcpy - .assume adl=1 - -; void *memcpy( void *dest, const void *src, size_t count ); - -_memcpy equ 0000A4h + .def _memcpy
+ .assume adl=1
+
+; void *memcpy( void *dest, const void *src, size_t count );
+
+_memcpy equ 0000A4h
diff --git a/frontends/calculator/CEdev/lib/shared/memmove.src b/frontends/calculator/CEdev/lib/shared/memmove.src index 4a219cd..31d3ce9 100644 --- a/frontends/calculator/CEdev/lib/shared/memmove.src +++ b/frontends/calculator/CEdev/lib/shared/memmove.src @@ -1,6 +1,6 @@ - .def _memmove - .assume adl=1 - -; void *memmove(void *dest, const void *src, size_t count); - -_memmove equ 0000A8h + .def _memmove
+ .assume adl=1
+
+; void *memmove(void *dest, const void *src, size_t count);
+
+_memmove equ 0000A8h
diff --git a/frontends/calculator/CEdev/lib/shared/memset.src b/frontends/calculator/CEdev/lib/shared/memset.src index 2ff1317..f64608c 100644 --- a/frontends/calculator/CEdev/lib/shared/memset.src +++ b/frontends/calculator/CEdev/lib/shared/memset.src @@ -1,26 +1,26 @@ - .def _memset - .assume adl=1 - -; void *memset(void *dest, int c, size_t count); - -_memset: - pop iy - pop hl - pop de - pop bc - push bc - push de - push hl - push iy - cpi - add hl,bc - ret c - dec hl - ld (hl),e - ret po - push hl - pop de - dec de - lddr - ret - + .def _memset
+ .assume adl=1
+
+; void *memset(void *dest, int c, size_t count);
+
+_memset:
+ pop iy
+ pop hl
+ pop de
+ pop bc
+ push bc
+ push de
+ push hl
+ push iy
+ cpi
+ add hl,bc
+ ret c
+ dec hl
+ ld (hl),e
+ ret po
+ push hl
+ pop de
+ dec de
+ lddr
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/os.src b/frontends/calculator/CEdev/lib/shared/os.src index 23e0852..76fd462 100644 --- a/frontends/calculator/CEdev/lib/shared/os.src +++ b/frontends/calculator/CEdev/lib/shared/os.src @@ -1,14 +1,14 @@ -; --- -; call an os or bootcode routine -; --- - - .def __OS - .assume adl=1 - -__OS: - pop de - pop hl - push hl - push de - ld iy,13631616 - jp (hl) +; ---
+; call an os or bootcode routine
+; ---
+
+ .def __OS
+ .assume adl=1
+
+__OS:
+ pop de
+ pop hl
+ push hl
+ push de
+ ld iy,13631616
+ jp (hl)
diff --git a/frontends/calculator/CEdev/lib/shared/os_textbuffer.src b/frontends/calculator/CEdev/lib/shared/os_textbuffer.src index 0f3c106..f8462c7 100644 --- a/frontends/calculator/CEdev/lib/shared/os_textbuffer.src +++ b/frontends/calculator/CEdev/lib/shared/os_textbuffer.src @@ -1,22 +1,22 @@ -; --- -; enables / disables homescreen text buffering which can destroy bss / heap -; --- - - .def _os_DisableHomeTextBuffer - .def _os_EnableHomeTextBuffer - .assume adl=1 - -_os_DisableHomeTextBuffer: - ld iy,$d00080 - res 1,(iy + $0d) ; no text buffer - res 3,(iy + $4a) ; use first shadow buffer - set 5,(iy + $4c) ; only display - ret - -_os_EnableHomeTextBuffer: - ld iy,$d00080 - set 1,(iy + $0d) ; use text buffer - res 3,(iy + $4a) ; use first shadow buffer - res 5,(iy + $4c) ; use shadow buffer - ret - +; ---
+; enables / disables homescreen text buffering which can destroy bss / heap
+; ---
+
+ .def _os_DisableHomeTextBuffer
+ .def _os_EnableHomeTextBuffer
+ .assume adl=1
+
+_os_DisableHomeTextBuffer:
+ ld iy,$d00080
+ res 1,(iy + $0d) ; no text buffer
+ res 3,(iy + $4a) ; use first shadow buffer
+ set 5,(iy + $4c) ; only display
+ ret
+
+_os_EnableHomeTextBuffer:
+ ld iy,$d00080
+ set 1,(iy + $0d) ; use text buffer
+ res 3,(iy + $4a) ; use first shadow buffer
+ res 5,(iy + $4c) ; use shadow buffer
+ ret
+
diff --git a/frontends/calculator/CEdev/lib/shared/rand.src b/frontends/calculator/CEdev/lib/shared/rand.src index ea569cf..df14c3a 100644 --- a/frontends/calculator/CEdev/lib/shared/rand.src +++ b/frontends/calculator/CEdev/lib/shared/rand.src @@ -1,13 +1,13 @@ - .ref _random - .def _rand - .assume adl=1 - -; int rand(void); - -_rand: - call _random - ld de,8388608 - sbc hl,de - ret p - add hl,de - ret + .ref _random
+ .def _rand
+ .assume adl=1
+
+; int rand(void);
+
+_rand:
+ call _random
+ ld de,8388608
+ sbc hl,de
+ ret p
+ add hl,de
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/random.src b/frontends/calculator/CEdev/lib/shared/random.src index ede9051..5381840 100644 --- a/frontends/calculator/CEdev/lib/shared/random.src +++ b/frontends/calculator/CEdev/lib/shared/random.src @@ -1,110 +1,110 @@ -; --- -; uint32_t random(void) -; --- - - .def _random - .def __state - .assume adl=1 - -; https://github.com/MersenneTwister-Lab/XSadd/blob/master/xsadd.h#L75 -; using shift parameters (19, 21, 8) instead of (15, 18, 11) - -; uint32_t xsadd(uint32_t state[static 4]) -; { -; uint32_t s0, s1, s2, t0, t1, t2, t3, z, result; -; t0 = state[0]; -; state[0] = state[1]; state[1] = state[2]; state[2] = state[3]; -; s0 = t0 << 19; -; t1 = t0 ^ s0; -; s1 = t1 >> 21; -; t2 = t1 ^ s1; -; z = state[3]; -; s2 = z << 8; -; t3 = t2 ^ s2; -; state[3] = t3; -; result = t3 + state[2]; -; return result; -; } - - segment data -__state: - dl 0d0e0f10h,090a0b0ch,05060708h,01020304h - - segment code -_random: -; Read state[0] and perform state shifting. - ld iy,__state ; iy = &state[0] - ld hl,(iy+0*4+0) ; hl = hl(state[0]) - push hl - ld hl,(iy+0*4+2) ; hl = eu(state[0]) - push hl - lea hl,iy+1*4 ; hl = &state[1] - lea de,iy+0*4 ; de = &state[0] - ld bc,3*4 - ldir ; state[0] = state[1] - ; state[1] = state[2] - ; state[2] = state[3] - pop bc - pop de ; bcde = state[0] == t0 -; -; s0 = t0 << 19 ==> s0h == 0 ==> t1h = t0h -; s0l == 0 ==> t1l = t0l -; -; s1 = t1 >> 21 ==> s1e == 0 ==> t2e = t1e -; s1u == 0 ==> t2u = t1u -; -; s2 = z << 8 ==> s2e == zu ==> t3e == t2e ^ s2e == t1e ^ s2e == t0e ^ s0e ^ s2e -; s2u == zh ==> t3u == t2u ^ s2u == t1u ^ s2u == t0u ^ s0u ^ s2u -; s2h == zl ==> t3h == t2h ^ s2h == t1h ^ s1h ^ s2h == t0h ^ s1h ^ s2h -; s2l == 0 ==> t3l == t2l == t1l ^ s1l == t0l ^ s1l -; -; Calculate s0. - ld h,d - ld l,e ; hl = t0hl == t0 << 16 - add hl,hl - add hl,hl - add hl,hl ; hl = t0 << 19 = s0eu - ; h = s0e - ; l = s0u -; Calculate t1e and t3e. - ld a,b ; a = t0e - xor a,h ; a = t0e ^ s0e == t1e - ld h,a ; h = t1e - xor a,(iy+3*4+2) ; a = t1e ^ zu == t2e ^ s2e == t3e - ld (iy+3*4+3),a ; e(state[3]) = t3e - ld b,a ; b = t3e -; Calculate t1u and t3u. - ld a,c ; a = t0u - xor a,l ; a = t0u ^ s0u == t1u - ld l,a ; l = t1u - ; hl = t1eu == t1 >> 16 - xor a,(iy+3*4+1) ; a = t1u ^ zh == t2u ^ s2u == t3u - ld (iy+3*4+2),a ; u(state[3]) = t3u -; Calculate s1. - xor a,a ; a = 0 - add.s hl,hl - adc a,a - add.s hl,hl - adc a,a - add.s hl,hl - adc a,a ; ahl = (t1 >> 16) << 3 - ; ah = ((t1 >> 16) << 3) >> 8 == t1 >> 21 == s1hl - ; a = s1h - ; h = s1l -; Calculate t3h. - xor a,d ; a = s1h ^ t0h === s1h ^ t1h == t2h - xor a,(iy+3*4+0) ; a = t2h ^ zl == t2h ^ s2h == t3h - ld (iy+3*4+1),a ; h(state[3]) = t3h -; Calculate t3l. - ld a,e ; a = t0l == t1l - xor a,h ; a = t1l ^ s1l == t2l == t3l - ld (iy+3*4+0),a ; l(state[3]) = t3l -; Calculate result. - ld hl,(iy+3*4) - ld a,b ; auhl = t3 - ld de,(iy+2*4) - ld c,(iy+2*4+3) ; cude = state[2] - add hl,de - adc a,c ; auhl = t3 + state[2] = result - ld e,a ; euhl = result - ret +; ---
+; uint32_t random(void)
+; ---
+
+ .def _random
+ .def __state
+ .assume adl=1
+
+; https://github.com/MersenneTwister-Lab/XSadd/blob/master/xsadd.h#L75
+; using shift parameters (19, 21, 8) instead of (15, 18, 11)
+
+; uint32_t xsadd(uint32_t state[static 4])
+; {
+; uint32_t s0, s1, s2, t0, t1, t2, t3, z, result;
+; t0 = state[0];
+; state[0] = state[1]; state[1] = state[2]; state[2] = state[3];
+; s0 = t0 << 19;
+; t1 = t0 ^ s0;
+; s1 = t1 >> 21;
+; t2 = t1 ^ s1;
+; z = state[3];
+; s2 = z << 8;
+; t3 = t2 ^ s2;
+; state[3] = t3;
+; result = t3 + state[2];
+; return result;
+; }
+
+ segment data
+__state:
+ dl 0d0e0f10h,090a0b0ch,05060708h,01020304h
+
+ segment code
+_random:
+; Read state[0] and perform state shifting.
+ ld iy,__state ; iy = &state[0]
+ ld hl,(iy+0*4+0) ; hl = hl(state[0])
+ push hl
+ ld hl,(iy+0*4+2) ; hl = eu(state[0])
+ push hl
+ lea hl,iy+1*4 ; hl = &state[1]
+ lea de,iy+0*4 ; de = &state[0]
+ ld bc,3*4
+ ldir ; state[0] = state[1]
+ ; state[1] = state[2]
+ ; state[2] = state[3]
+ pop bc
+ pop de ; bcde = state[0] == t0
+;
+; s0 = t0 << 19 ==> s0h == 0 ==> t1h = t0h
+; s0l == 0 ==> t1l = t0l
+;
+; s1 = t1 >> 21 ==> s1e == 0 ==> t2e = t1e
+; s1u == 0 ==> t2u = t1u
+;
+; s2 = z << 8 ==> s2e == zu ==> t3e == t2e ^ s2e == t1e ^ s2e == t0e ^ s0e ^ s2e
+; s2u == zh ==> t3u == t2u ^ s2u == t1u ^ s2u == t0u ^ s0u ^ s2u
+; s2h == zl ==> t3h == t2h ^ s2h == t1h ^ s1h ^ s2h == t0h ^ s1h ^ s2h
+; s2l == 0 ==> t3l == t2l == t1l ^ s1l == t0l ^ s1l
+;
+; Calculate s0.
+ ld h,d
+ ld l,e ; hl = t0hl == t0 << 16
+ add hl,hl
+ add hl,hl
+ add hl,hl ; hl = t0 << 19 = s0eu
+ ; h = s0e
+ ; l = s0u
+; Calculate t1e and t3e.
+ ld a,b ; a = t0e
+ xor a,h ; a = t0e ^ s0e == t1e
+ ld h,a ; h = t1e
+ xor a,(iy+3*4+2) ; a = t1e ^ zu == t2e ^ s2e == t3e
+ ld (iy+3*4+3),a ; e(state[3]) = t3e
+ ld b,a ; b = t3e
+; Calculate t1u and t3u.
+ ld a,c ; a = t0u
+ xor a,l ; a = t0u ^ s0u == t1u
+ ld l,a ; l = t1u
+ ; hl = t1eu == t1 >> 16
+ xor a,(iy+3*4+1) ; a = t1u ^ zh == t2u ^ s2u == t3u
+ ld (iy+3*4+2),a ; u(state[3]) = t3u
+; Calculate s1.
+ xor a,a ; a = 0
+ add.s hl,hl
+ adc a,a
+ add.s hl,hl
+ adc a,a
+ add.s hl,hl
+ adc a,a ; ahl = (t1 >> 16) << 3
+ ; ah = ((t1 >> 16) << 3) >> 8 == t1 >> 21 == s1hl
+ ; a = s1h
+ ; h = s1l
+; Calculate t3h.
+ xor a,d ; a = s1h ^ t0h === s1h ^ t1h == t2h
+ xor a,(iy+3*4+0) ; a = t2h ^ zl == t2h ^ s2h == t3h
+ ld (iy+3*4+1),a ; h(state[3]) = t3h
+; Calculate t3l.
+ ld a,e ; a = t0l == t1l
+ xor a,h ; a = t1l ^ s1l == t2l == t3l
+ ld (iy+3*4+0),a ; l(state[3]) = t3l
+; Calculate result.
+ ld hl,(iy+3*4)
+ ld a,b ; auhl = t3
+ ld de,(iy+2*4)
+ ld c,(iy+2*4+3) ; cude = state[2]
+ add hl,de
+ adc a,c ; auhl = t3 + state[2] = result
+ ld e,a ; euhl = result
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/removeallbreakpoints.src b/frontends/calculator/CEdev/lib/shared/removeallbreakpoints.src index ddae792..effb0d2 100644 --- a/frontends/calculator/CEdev/lib/shared/removeallbreakpoints.src +++ b/frontends/calculator/CEdev/lib/shared/removeallbreakpoints.src @@ -1,12 +1,12 @@ -; --- -; remove all breakpoints -; --- - - .def _dbg_RemoveAllBreakpoints - .assume adl=1 - -_dbg_RemoveAllBreakpoints: - scf - sbc hl,hl - ld (hl),9 - ret +; ---
+; remove all breakpoints
+; ---
+
+ .def _dbg_RemoveAllBreakpoints
+ .assume adl=1
+
+_dbg_RemoveAllBreakpoints:
+ scf
+ sbc hl,hl
+ ld (hl),9
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/removeallwatchpoints.src b/frontends/calculator/CEdev/lib/shared/removeallwatchpoints.src index 7171ba4..c5b86bb 100644 --- a/frontends/calculator/CEdev/lib/shared/removeallwatchpoints.src +++ b/frontends/calculator/CEdev/lib/shared/removeallwatchpoints.src @@ -1,12 +1,12 @@ -; --- -; remove all watchpoints -; --- - - .def _dbg_RemoveAllWatchpoints - .assume adl=1 - -_dbg_RemoveAllWatchpoints: - scf - sbc hl,hl - ld (hl),10 - ret +; ---
+; remove all watchpoints
+; ---
+
+ .def _dbg_RemoveAllWatchpoints
+ .assume adl=1
+
+_dbg_RemoveAllWatchpoints:
+ scf
+ sbc hl,hl
+ ld (hl),10
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/removebreakpoint.src b/frontends/calculator/CEdev/lib/shared/removebreakpoint.src index d2c4b9b..a7094da 100644 --- a/frontends/calculator/CEdev/lib/shared/removebreakpoint.src +++ b/frontends/calculator/CEdev/lib/shared/removebreakpoint.src @@ -1,16 +1,16 @@ -; --- -; remove breakpoint -; --- - - .def _dbg_RemoveBreakpoint - .assume adl=1 - -_dbg_RemoveBreakpoint: - pop hl - pop de - push de - push hl - scf - sbc hl,hl - ld (hl),4 - ret +; ---
+; remove breakpoint
+; ---
+
+ .def _dbg_RemoveBreakpoint
+ .assume adl=1
+
+_dbg_RemoveBreakpoint:
+ pop hl
+ pop de
+ push de
+ push hl
+ scf
+ sbc hl,hl
+ ld (hl),4
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/removewatchpoint.src b/frontends/calculator/CEdev/lib/shared/removewatchpoint.src index a096d15..eb39c92 100644 --- a/frontends/calculator/CEdev/lib/shared/removewatchpoint.src +++ b/frontends/calculator/CEdev/lib/shared/removewatchpoint.src @@ -1,16 +1,16 @@ -; --- -; remove watchpoint -; --- - - .def _dbg_RemoveWatchpoint - .assume adl=1 - -_dbg_RemoveWatchpoint: - pop hl - pop de - push de - push hl - scf - sbc hl,hl - ld (hl),8 - ret +; ---
+; remove watchpoint
+; ---
+
+ .def _dbg_RemoveWatchpoint
+ .assume adl=1
+
+_dbg_RemoveWatchpoint:
+ pop hl
+ pop de
+ push de
+ push hl
+ scf
+ sbc hl,hl
+ ld (hl),8
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/round.src b/frontends/calculator/CEdev/lib/shared/round.src index e78e237..99573e9 100644 --- a/frontends/calculator/CEdev/lib/shared/round.src +++ b/frontends/calculator/CEdev/lib/shared/round.src @@ -1,44 +1,44 @@ - .def _round - .ref __frameset0 - .ref __fcmp - .ref __fadd - .ref __fsub - .ref _floor - .ref _ceil - .assume adl=1 - -_round: - call __frameset0 - ld hl,(ix+6) - ld e,(ix+9) - ld bc,0 - xor a,a - call __fcmp - push af - or a,a - sbc hl,hl - ld e,63 - ld bc,(ix+6) - pop af - ld a,(ix+9) - jp m,IsLessZero - call __fadd - or a,a - sbc hl,hl - ld l,a - push bc - push hl - call _floor - jr Finish -IsLessZero: - call __fsub - or a,a - sbc hl,hl - ld l,a - push bc - push hl - call _ceil -Finish: - ld sp,ix - pop ix - ret + .def _round
+ .ref __frameset0
+ .ref __fcmp
+ .ref __fadd
+ .ref __fsub
+ .ref _floor
+ .ref _ceil
+ .assume adl=1
+
+_round:
+ call __frameset0
+ ld hl,(ix+6)
+ ld e,(ix+9)
+ ld bc,0
+ xor a,a
+ call __fcmp
+ push af
+ or a,a
+ sbc hl,hl
+ ld e,63
+ ld bc,(ix+6)
+ pop af
+ ld a,(ix+9)
+ jp m,IsLessZero
+ call __fadd
+ or a,a
+ sbc hl,hl
+ ld l,a
+ push bc
+ push hl
+ call _floor
+ jr Finish
+IsLessZero:
+ call __fsub
+ or a,a
+ sbc hl,hl
+ ld l,a
+ push bc
+ push hl
+ call _ceil
+Finish:
+ ld sp,ix
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/sand.src b/frontends/calculator/CEdev/lib/shared/sand.src index a39e220..401ffc6 100644 --- a/frontends/calculator/CEdev/lib/shared/sand.src +++ b/frontends/calculator/CEdev/lib/shared/sand.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short AND. -; Input: -; Operand1: -; hl : 16 bit -; -; Operand2: -; bc : 16 bit -; -; Output: -; Result: hl : 16 bit -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __sand - .assume adl=1 - -__sand equ 000200h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short AND.
+; Input:
+; Operand1:
+; hl : 16 bit
+;
+; Operand2:
+; bc : 16 bit
+;
+; Output:
+; Result: hl : 16 bit
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __sand
+ .assume adl=1
+
+__sand equ 000200h
diff --git a/frontends/calculator/CEdev/lib/shared/sbrk.src b/frontends/calculator/CEdev/lib/shared/sbrk.src index ab1cf1b..6410631 100644 --- a/frontends/calculator/CEdev/lib/shared/sbrk.src +++ b/frontends/calculator/CEdev/lib/shared/sbrk.src @@ -1,49 +1,49 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Heap allocation routine s_sbrk -; Input: -; argument : 24 bit - number of bytes requested -; -; Output: -; Result: HL: 24 bit address of memory allocated -; HL = 0 if no memory available - -; Registers Used: -; -;------------------------------------------------------------------------- - .assume adl=1 - .ref __heapbot - .ref __heaptop - .def __s_sbrk - - SEGMENT DATA -__sbrkbase: - .trio __heapbot - - SEGMENT CODE -__s_sbrk: - ld hl,3 - add hl,sp - ld hl,(hl) ;nbytes - ld de,(__sbrkbase) - add hl,de - jr c,_fail - - ; fail if hl >= sp. - ; hl is now, or will be, the next un-allocated address = minimal value - ; for sp that will not corrupt allocated data or that writing to - ; allocated data may corrupt the stack. - ; Actually, if hl is anywhere close to sp we're probably in trouble :( - - push hl - sbc hl,sp - pop hl - jr nc,_fail -_ok: - ex hl,de - ld (__sbrkbase),de - ret -_fail: - or a,a - sbc hl,hl - ret +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Heap allocation routine s_sbrk
+; Input:
+; argument : 24 bit - number of bytes requested
+;
+; Output:
+; Result: HL: 24 bit address of memory allocated
+; HL = 0 if no memory available
+
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .assume adl=1
+ .ref __heapbot
+ .ref __heaptop
+ .def __s_sbrk
+
+ SEGMENT DATA
+__sbrkbase:
+ .trio __heapbot
+
+ SEGMENT CODE
+__s_sbrk:
+ ld hl,3
+ add hl,sp
+ ld hl,(hl) ;nbytes
+ ld de,(__sbrkbase)
+ add hl,de
+ jr c,_fail
+
+ ; fail if hl >= sp.
+ ; hl is now, or will be, the next un-allocated address = minimal value
+ ; for sp that will not corrupt allocated data or that writing to
+ ; allocated data may corrupt the stack.
+ ; Actually, if hl is anywhere close to sp we're probably in trouble :(
+
+ push hl
+ sbc hl,sp
+ pop hl
+ jr nc,_fail
+_ok:
+ ex hl,de
+ ld (__sbrkbase),de
+ ret
+_fail:
+ or a,a
+ sbc hl,hl
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/scmpzero.src b/frontends/calculator/CEdev/lib/shared/scmpzero.src index 5c62a13..5b54941 100644 --- a/frontends/calculator/CEdev/lib/shared/scmpzero.src +++ b/frontends/calculator/CEdev/lib/shared/scmpzero.src @@ -1,16 +1,16 @@ -; (c) Copyright 2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Set flag for comparison of 16-bit scalar with constant value zero -; Input: -; Operand1: HL register -; -; Output: -; Result: f register -; -; Registers Used: -; None -;------------------------------------------------------------------------- - .def __scmpzero - .assume adl=1 - -__scmpzero equ 000204h +; (c) Copyright 2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Set flag for comparison of 16-bit scalar with constant value zero
+; Input:
+; Operand1: HL register
+;
+; Output:
+; Result: f register
+;
+; Registers Used:
+; None
+;-------------------------------------------------------------------------
+ .def __scmpzero
+ .assume adl=1
+
+__scmpzero equ 000204h
diff --git a/frontends/calculator/CEdev/lib/shared/sdivs.src b/frontends/calculator/CEdev/lib/shared/sdivs.src index 75cda77..e91692c 100644 --- a/frontends/calculator/CEdev/lib/shared/sdivs.src +++ b/frontends/calculator/CEdev/lib/shared/sdivs.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Division Signed -; Input: -; Operand1: -; hl : 16 bits x -; -; Operand2: -; bc : 16 bits y -; -; Output: -; Result: hl : 16 bits -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __sdivs - .assume adl=1 - -__sdivs equ 000208h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Division Signed
+; Input:
+; Operand1:
+; hl : 16 bits x
+;
+; Operand2:
+; bc : 16 bits y
+;
+; Output:
+; Result: hl : 16 bits
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __sdivs
+ .assume adl=1
+
+__sdivs equ 000208h
diff --git a/frontends/calculator/CEdev/lib/shared/sdivu.src b/frontends/calculator/CEdev/lib/shared/sdivu.src index 2002728..9cde056 100644 --- a/frontends/calculator/CEdev/lib/shared/sdivu.src +++ b/frontends/calculator/CEdev/lib/shared/sdivu.src @@ -1,21 +1,21 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Division Unsigned -; Input: -; Operand1: -; hl : 16 bits -; -; Operand2: -; bc : 16 bits -; -; Output: -; Result: hl : 16 bits -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __sdivu - .assume adl=1 - -__sdivu equ 00020Ch - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Division Unsigned
+; Input:
+; Operand1:
+; hl : 16 bits
+;
+; Operand2:
+; bc : 16 bits
+;
+; Output:
+; Result: hl : 16 bits
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __sdivu
+ .assume adl=1
+
+__sdivu equ 00020Ch
+
diff --git a/frontends/calculator/CEdev/lib/shared/seqcase.src b/frontends/calculator/CEdev/lib/shared/seqcase.src index 5c4a084..fda01b3 100644 --- a/frontends/calculator/CEdev/lib/shared/seqcase.src +++ b/frontends/calculator/CEdev/lib/shared/seqcase.src @@ -1,25 +1,25 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; Returns to case label -; Data at Return Address: -; DW numCases 0 -; DW24 startValue 2 -; DW24 Lab1 5 -; DW24 Lab2 8 -; ... -; DW24 defaultLab 5+3*numCases -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __seqcase - .assume adl=1 - +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+; Returns to case label
+; Data at Return Address:
+; DW numCases 0
+; DW24 startValue 2
+; DW24 Lab1 5
+; DW24 Lab2 8
+; ...
+; DW24 defaultLab 5+3*numCases
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __seqcase
+ .assume adl=1
+
__seqcase equ 000210h
\ No newline at end of file diff --git a/frontends/calculator/CEdev/lib/shared/seqcased.src b/frontends/calculator/CEdev/lib/shared/seqcased.src index d6dcea1..7a40003 100644 --- a/frontends/calculator/CEdev/lib/shared/seqcased.src +++ b/frontends/calculator/CEdev/lib/shared/seqcased.src @@ -1,26 +1,26 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; CASE branch resolution. -; -; Input: -; Operand3: -; hl : 24 bit value to match in table -; -; Output: -; Result: hl : 24 bit address of case jp to take -; Registers Used: -; -; Data at Return Address: -; JP (HL) 0 -; DW numCases 1 -; DW24 startValue 3 -; DW24 Lab1 6 -; DW24 Lab2 9 -; ... -; DW24 defaultLab 6+3*numCases -; -;------------------------------------------------------------------------- - .def __seqcaseD - .assume adl=1 - -__seqcaseD equ 000214h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; CASE branch resolution.
+;
+; Input:
+; Operand3:
+; hl : 24 bit value to match in table
+;
+; Output:
+; Result: hl : 24 bit address of case jp to take
+; Registers Used:
+;
+; Data at Return Address:
+; JP (HL) 0
+; DW numCases 1
+; DW24 startValue 3
+; DW24 Lab1 6
+; DW24 Lab2 9
+; ...
+; DW24 defaultLab 6+3*numCases
+;
+;-------------------------------------------------------------------------
+ .def __seqcaseD
+ .assume adl=1
+
+__seqcaseD equ 000214h
diff --git a/frontends/calculator/CEdev/lib/shared/setbreakpoint.src b/frontends/calculator/CEdev/lib/shared/setbreakpoint.src index 5a1e929..6fd03d5 100644 --- a/frontends/calculator/CEdev/lib/shared/setbreakpoint.src +++ b/frontends/calculator/CEdev/lib/shared/setbreakpoint.src @@ -1,16 +1,16 @@ -; --- -; set breakpoint -; --- - - .def _dbg_SetBreakpoint - .assume adl=1 - -_dbg_SetBreakpoint: - pop hl - pop de - push de - push hl - scf - sbc hl,hl - ld (hl),3 - ret +; ---
+; set breakpoint
+; ---
+
+ .def _dbg_SetBreakpoint
+ .assume adl=1
+
+_dbg_SetBreakpoint:
+ pop hl
+ pop de
+ push de
+ push hl
+ scf
+ sbc hl,hl
+ ld (hl),3
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/setflag.src b/frontends/calculator/CEdev/lib/shared/setflag.src index b710b95..928cfdd 100644 --- a/frontends/calculator/CEdev/lib/shared/setflag.src +++ b/frontends/calculator/CEdev/lib/shared/setflag.src @@ -1,22 +1,22 @@ -; (c) Copyright 2007-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Set Sign flag for signed comparison -; s <-- s xor v -; Input: -; Operand1: f register -; -; Output: -; Result: updated f register -; -; Registers Used: -; None -;------------------------------------------------------------------------- -; if ( V == 0) -; S = S xor 0 -> S = S -; if ( V != 0) -; S = S xor V -;------------------------------------------------------------------------- - .def __setflag - .assume adl=1 - -__setflag equ 000218h +; (c) Copyright 2007-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Set Sign flag for signed comparison
+; s <-- s xor v
+; Input:
+; Operand1: f register
+;
+; Output:
+; Result: updated f register
+;
+; Registers Used:
+; None
+;-------------------------------------------------------------------------
+; if ( V == 0)
+; S = S xor 0 -> S = S
+; if ( V != 0)
+; S = S xor V
+;-------------------------------------------------------------------------
+ .def __setflag
+ .assume adl=1
+
+__setflag equ 000218h
diff --git a/frontends/calculator/CEdev/lib/shared/setjmp.src b/frontends/calculator/CEdev/lib/shared/setjmp.src index 9bc7c37..607a6eb 100644 --- a/frontends/calculator/CEdev/lib/shared/setjmp.src +++ b/frontends/calculator/CEdev/lib/shared/setjmp.src @@ -1,6 +1,6 @@ - .def _setjmp - .assume adl=1 - -; int setjmp(jmp_buf env); - -_setjmp equ 0000B8h + .def _setjmp
+ .assume adl=1
+
+; int setjmp(jmp_buf env);
+
+_setjmp equ 0000B8h
diff --git a/frontends/calculator/CEdev/lib/shared/setreadwatchpoint.src b/frontends/calculator/CEdev/lib/shared/setreadwatchpoint.src index 7ada983..c4c57aa 100644 --- a/frontends/calculator/CEdev/lib/shared/setreadwatchpoint.src +++ b/frontends/calculator/CEdev/lib/shared/setreadwatchpoint.src @@ -1,18 +1,18 @@ -; --- -; set read watchpoint -; --- - - .def _dbg_SetReadWatchpoint - .assume adl=1 - -_dbg_SetReadWatchpoint: - pop hl - pop de - pop bc - push bc - push de - push hl - scf - sbc hl,hl - ld (hl),5 - ret +; ---
+; set read watchpoint
+; ---
+
+ .def _dbg_SetReadWatchpoint
+ .assume adl=1
+
+_dbg_SetReadWatchpoint:
+ pop hl
+ pop de
+ pop bc
+ push bc
+ push de
+ push hl
+ scf
+ sbc hl,hl
+ ld (hl),5
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/setreadwritewatchpoint.src b/frontends/calculator/CEdev/lib/shared/setreadwritewatchpoint.src index f303929..ba7a44d 100644 --- a/frontends/calculator/CEdev/lib/shared/setreadwritewatchpoint.src +++ b/frontends/calculator/CEdev/lib/shared/setreadwritewatchpoint.src @@ -1,18 +1,18 @@ -; --- -; set write watchpoint -; --- - - .def _dbg_SetReadWriteWatchpoint - .assume adl=1 - -_dbg_SetReadWriteWatchpoint: - pop hl - pop de - pop bc - push bc - push de - push hl - scf - sbc hl,hl - ld (hl),7 - ret +; ---
+; set write watchpoint
+; ---
+
+ .def _dbg_SetReadWriteWatchpoint
+ .assume adl=1
+
+_dbg_SetReadWriteWatchpoint:
+ pop hl
+ pop de
+ pop bc
+ push bc
+ push de
+ push hl
+ scf
+ sbc hl,hl
+ ld (hl),7
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/setwatchpoint.src b/frontends/calculator/CEdev/lib/shared/setwatchpoint.src index bf148d4..a46bc74 100644 --- a/frontends/calculator/CEdev/lib/shared/setwatchpoint.src +++ b/frontends/calculator/CEdev/lib/shared/setwatchpoint.src @@ -1,18 +1,18 @@ -; --- -; set watchpoint -; --- - - .def _dbg_SetWatchpoint - .assume adl=1 - -_dbg_SetWatchpoint: - pop hl - pop de - pop bc - push bc - push de - push hl - scf - sbc hl,hl - ld (hl),11 - ret +; ---
+; set watchpoint
+; ---
+
+ .def _dbg_SetWatchpoint
+ .assume adl=1
+
+_dbg_SetWatchpoint:
+ pop hl
+ pop de
+ pop bc
+ push bc
+ push de
+ push hl
+ scf
+ sbc hl,hl
+ ld (hl),11
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/setwritewatchpoint.src b/frontends/calculator/CEdev/lib/shared/setwritewatchpoint.src index 62bb06f..42f8ef9 100644 --- a/frontends/calculator/CEdev/lib/shared/setwritewatchpoint.src +++ b/frontends/calculator/CEdev/lib/shared/setwritewatchpoint.src @@ -1,18 +1,18 @@ -; --- -; set write watchpoint -; --- - - .def _dbg_SetWriteWatchpoint - .assume adl=1 - -_dbg_SetWriteWatchpoint: - pop hl - pop de - pop bc - push bc - push de - push hl - scf - sbc hl,hl - ld (hl),6 - ret +; ---
+; set write watchpoint
+; ---
+
+ .def _dbg_SetWriteWatchpoint
+ .assume adl=1
+
+_dbg_SetWriteWatchpoint:
+ pop hl
+ pop de
+ pop bc
+ push bc
+ push de
+ push hl
+ scf
+ sbc hl,hl
+ ld (hl),6
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/sldix.src b/frontends/calculator/CEdev/lib/shared/sldix.src index 45c8006..9306541 100644 --- a/frontends/calculator/CEdev/lib/shared/sldix.src +++ b/frontends/calculator/CEdev/lib/shared/sldix.src @@ -1,17 +1,17 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; short load hl,(ix+nnnnnn) -; Input: -; Operand1: -; BC : 24-bit offset from ix -; -; Output: -; Result: hl : 16 bit -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __sldix - .assume adl=1 - -__sldix equ 00021Ch +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; short load hl,(ix+nnnnnn)
+; Input:
+; Operand1:
+; BC : 24-bit offset from ix
+;
+; Output:
+; Result: hl : 16 bit
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __sldix
+ .assume adl=1
+
+__sldix equ 00021Ch
diff --git a/frontends/calculator/CEdev/lib/shared/sldiy.src b/frontends/calculator/CEdev/lib/shared/sldiy.src index 2a820ce..a0e923e 100644 --- a/frontends/calculator/CEdev/lib/shared/sldiy.src +++ b/frontends/calculator/CEdev/lib/shared/sldiy.src @@ -1,18 +1,18 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; short load hl,(iy+nnnnnn) -; Input: -; Operand1: -; BC : 24-bit offset from iy -; -; Output: -; Result: hl : 16-bit -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __sldiy - .assume adl=1 - -__sldiy equ 000220h - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; short load hl,(iy+nnnnnn)
+; Input:
+; Operand1:
+; BC : 24-bit offset from iy
+;
+; Output:
+; Result: hl : 16-bit
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __sldiy
+ .assume adl=1
+
+__sldiy equ 000220h
+
diff --git a/frontends/calculator/CEdev/lib/shared/smuls.src b/frontends/calculator/CEdev/lib/shared/smuls.src index 4ac0260..f16bb98 100644 --- a/frontends/calculator/CEdev/lib/shared/smuls.src +++ b/frontends/calculator/CEdev/lib/shared/smuls.src @@ -1,21 +1,21 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Multiply Signed -; Input: -; Operand1: -; bc : 16 bits -; -; Operand2: -; hl : 16 bits -; -; Output: -; Result: hl : 16 bits -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __smuls - .assume adl=1 - -__smuls equ 000224h - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Multiply Signed
+; Input:
+; Operand1:
+; bc : 16 bits
+;
+; Operand2:
+; hl : 16 bits
+;
+; Output:
+; Result: hl : 16 bits
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __smuls
+ .assume adl=1
+
+__smuls equ 000224h
+
diff --git a/frontends/calculator/CEdev/lib/shared/smulu.src b/frontends/calculator/CEdev/lib/shared/smulu.src index 4433a62..aace92f 100644 --- a/frontends/calculator/CEdev/lib/shared/smulu.src +++ b/frontends/calculator/CEdev/lib/shared/smulu.src @@ -1,21 +1,21 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Multiply Unsigned -; Input: -; Operand1: -; BC : 16 bits -; -; Operand2: -; HL : 16 bits -; -; Output: -; Result: HL : 16 bits -; -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __smulu - .assume adl=1 - -__smulu equ 000228h - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Multiply Unsigned
+; Input:
+; Operand1:
+; BC : 16 bits
+;
+; Operand2:
+; HL : 16 bits
+;
+; Output:
+; Result: HL : 16 bits
+;
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __smulu
+ .assume adl=1
+
+__smulu equ 000228h
+
diff --git a/frontends/calculator/CEdev/lib/shared/sneg.src b/frontends/calculator/CEdev/lib/shared/sneg.src index 4a3fb47..6222cf2 100644 --- a/frontends/calculator/CEdev/lib/shared/sneg.src +++ b/frontends/calculator/CEdev/lib/shared/sneg.src @@ -1,16 +1,16 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short NEG. -; Input: -; Operand1: -; hl : 16 bit -; -; Output: -; Result: hl : 16 bit -; Registers Used: -; None -;------------------------------------------------------------------------- - .def __sneg - .assume adl=1 - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short NEG.
+; Input:
+; Operand1:
+; hl : 16 bit
+;
+; Output:
+; Result: hl : 16 bit
+; Registers Used:
+; None
+;-------------------------------------------------------------------------
+ .def __sneg
+ .assume adl=1
+
__sneg equ 00022Ch
\ No newline at end of file diff --git a/frontends/calculator/CEdev/lib/shared/snot.src b/frontends/calculator/CEdev/lib/shared/snot.src index 307da76..9a9cb26 100644 --- a/frontends/calculator/CEdev/lib/shared/snot.src +++ b/frontends/calculator/CEdev/lib/shared/snot.src @@ -1,16 +1,16 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short NOT. -; Input: -; Operand1: -; hl : 16 bit -; -; Output: -; Result: hl : 16 bit -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __snot - .assume adl=1 - -__snot equ 000230h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short NOT.
+; Input:
+; Operand1:
+; hl : 16 bit
+;
+; Output:
+; Result: hl : 16 bit
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __snot
+ .assume adl=1
+
+__snot equ 000230h
diff --git a/frontends/calculator/CEdev/lib/shared/sor.src b/frontends/calculator/CEdev/lib/shared/sor.src index 119a003..1e8968a 100644 --- a/frontends/calculator/CEdev/lib/shared/sor.src +++ b/frontends/calculator/CEdev/lib/shared/sor.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short OR. -; Input: -; Operand1: -; hl : 16 bit -; -; Operand2: -; bc : 16 bit -; -; Output: -; Result: hl : 16 bit -; hl OR bc -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __sor - .assume adl=1 - -__sor equ 000234h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short OR.
+; Input:
+; Operand1:
+; hl : 16 bit
+;
+; Operand2:
+; bc : 16 bit
+;
+; Output:
+; Result: hl : 16 bit
+; hl OR bc
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __sor
+ .assume adl=1
+
+__sor equ 000234h
diff --git a/frontends/calculator/CEdev/lib/shared/sprintf.src b/frontends/calculator/CEdev/lib/shared/sprintf.src index 7c09553..367e689 100644 --- a/frontends/calculator/CEdev/lib/shared/sprintf.src +++ b/frontends/calculator/CEdev/lib/shared/sprintf.src @@ -1,7 +1,7 @@ - .def _sprintf - .assume adl=1 - -; int sprintf (char * str, const char * format, ...); - -_sprintf equ 0000BCh - + .def _sprintf
+ .assume adl=1
+
+; int sprintf (char * str, const char * format, ...);
+
+_sprintf equ 0000BCh
+
diff --git a/frontends/calculator/CEdev/lib/shared/sqrtf.src b/frontends/calculator/CEdev/lib/shared/sqrtf.src index 563d151..f3d4214 100644 --- a/frontends/calculator/CEdev/lib/shared/sqrtf.src +++ b/frontends/calculator/CEdev/lib/shared/sqrtf.src @@ -1,37 +1,37 @@ -;-------------------------------------------------------------- -; -; IEEE Single precision square root -; Copyright 2003-2008 Zilog, Inc. -; -;-------------------------------------------------------------- -; -; INPUTS: -; Operand1: -; (stack) : 32 bit IEEE format -; -; OUTPUTS: -; Result: -; EuHL : 32 bit IEEE format result -; -; ALGORITHM: -; This algorithm is very similar to that used for binary -; division; readers should be familiar with that -; algorithm of repetitive compare/subtract, and shift. -; This algorithm uses the same concepts, except that the -; number compared/subtracted is 2*x+1, where 'x' is the -; developing result. Briefly, if 'y' is the input parameter, -; and 'x' is the result developed (and subtracted out) so -; far, then 'y - x^2' is the residual value. If the residual -; is greater than '2*x + 1', then we subtract that out, -; and add one to x; this means that the new residual is -; 'y - (x+1)^2'. Repetitively applied with shifting, 'x^2' -; approaches the value of 'y'. -; -; Registers Used: -; AF,BC,D -; -;-------------------------------------------------------------- - .def _sqrtf - .assume adl=1 - -_sqrtf equ 000298h +;--------------------------------------------------------------
+;
+; IEEE Single precision square root
+; Copyright 2003-2008 Zilog, Inc.
+;
+;--------------------------------------------------------------
+;
+; INPUTS:
+; Operand1:
+; (stack) : 32 bit IEEE format
+;
+; OUTPUTS:
+; Result:
+; EuHL : 32 bit IEEE format result
+;
+; ALGORITHM:
+; This algorithm is very similar to that used for binary
+; division; readers should be familiar with that
+; algorithm of repetitive compare/subtract, and shift.
+; This algorithm uses the same concepts, except that the
+; number compared/subtracted is 2*x+1, where 'x' is the
+; developing result. Briefly, if 'y' is the input parameter,
+; and 'x' is the result developed (and subtracted out) so
+; far, then 'y - x^2' is the residual value. If the residual
+; is greater than '2*x + 1', then we subtract that out,
+; and add one to x; this means that the new residual is
+; 'y - (x+1)^2'. Repetitively applied with shifting, 'x^2'
+; approaches the value of 'y'.
+;
+; Registers Used:
+; AF,BC,D
+;
+;--------------------------------------------------------------
+ .def _sqrtf
+ .assume adl=1
+
+_sqrtf equ 000298h
diff --git a/frontends/calculator/CEdev/lib/shared/srand.src b/frontends/calculator/CEdev/lib/shared/srand.src index bbcf8f2..cf19c1d 100644 --- a/frontends/calculator/CEdev/lib/shared/srand.src +++ b/frontends/calculator/CEdev/lib/shared/srand.src @@ -1,12 +1,12 @@ - .ref __setstate - .def _srand - .assume adl=1 - -; void srand(unsigned int seed); - -_srand: - pop bc - ex (sp),hl - push bc - xor a,a - jp __setstate + .ref __setstate
+ .def _srand
+ .assume adl=1
+
+; void srand(unsigned int seed);
+
+_srand:
+ pop bc
+ ex (sp),hl
+ push bc
+ xor a,a
+ jp __setstate
diff --git a/frontends/calculator/CEdev/lib/shared/srandom.src b/frontends/calculator/CEdev/lib/shared/srandom.src index 0aa5189..ffcd54f 100644 --- a/frontends/calculator/CEdev/lib/shared/srandom.src +++ b/frontends/calculator/CEdev/lib/shared/srandom.src @@ -1,29 +1,29 @@ -; --- -; void srandom(uint32_t seed) -; --- - - .ref __state - .def _srandom - .def __setstate - .assume adl=1 - -_MemClear equ 00210E0h - -_srandom: - pop bc - pop de - ex (sp),hl ; lude = seed - push de - push bc - ex de,hl - ld a,e ; auhl = seed -__setstate: - ld (__state),hl - ld hl,__state+3 - ld (hl),a - ld b,12 -__setstateloop: - inc hl - ld (hl),b - djnz __setstateloop - ret +; ---
+; void srandom(uint32_t seed)
+; ---
+
+ .ref __state
+ .def _srandom
+ .def __setstate
+ .assume adl=1
+
+_MemClear equ 00210E0h
+
+_srandom:
+ pop bc
+ pop de
+ ex (sp),hl ; lude = seed
+ push de
+ push bc
+ ex de,hl
+ ld a,e ; auhl = seed
+__setstate:
+ ld (__state),hl
+ ld hl,__state+3
+ ld (hl),a
+ ld b,12
+__setstateloop:
+ inc hl
+ ld (hl),b
+ djnz __setstateloop
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/srems.src b/frontends/calculator/CEdev/lib/shared/srems.src index 54b2907..1cc74a2 100644 --- a/frontends/calculator/CEdev/lib/shared/srems.src +++ b/frontends/calculator/CEdev/lib/shared/srems.src @@ -1,21 +1,21 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Modulus Signed -; Input: -; Operand1: -; hl : 16 bits -; -; Operand2: -; bc : 16 bits -; -; Output: -; Result: hl : 16 bits -; -; Registers Used: -; -;------------------------------------------------------------------------- - .ref __irems - .def __srems - .assume adl=1 - -__srems equ 000238h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Modulus Signed
+; Input:
+; Operand1:
+; hl : 16 bits
+;
+; Operand2:
+; bc : 16 bits
+;
+; Output:
+; Result: hl : 16 bits
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .ref __irems
+ .def __srems
+ .assume adl=1
+
+__srems equ 000238h
diff --git a/frontends/calculator/CEdev/lib/shared/sremu.src b/frontends/calculator/CEdev/lib/shared/sremu.src index 6ecd4aa..d8ca078 100644 --- a/frontends/calculator/CEdev/lib/shared/sremu.src +++ b/frontends/calculator/CEdev/lib/shared/sremu.src @@ -1,21 +1,21 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Modulus Unsigned -; Input: -; Operand1: -; hl : 16 bits -; -; Operand2: -; bc : 16 bits -; -; Output: -; Result: hl : 16 bits -; -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __sremu - .ref __iremu - .assume adl=1 - -__sremu equ 00023Ch +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Modulus Unsigned
+; Input:
+; Operand1:
+; hl : 16 bits
+;
+; Operand2:
+; bc : 16 bits
+;
+; Output:
+; Result: hl : 16 bits
+;
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __sremu
+ .ref __iremu
+ .assume adl=1
+
+__sremu equ 00023Ch
diff --git a/frontends/calculator/CEdev/lib/shared/sshl.src b/frontends/calculator/CEdev/lib/shared/sshl.src index cf5034d..1c10828 100644 --- a/frontends/calculator/CEdev/lib/shared/sshl.src +++ b/frontends/calculator/CEdev/lib/shared/sshl.src @@ -1,22 +1,22 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Shift Left -; Input: -; Operand1: -; BC : 16 bit number of bits to shift -; Assume B=0 C=shift count -; Operand2: -; HL : 16 bit value to be shifted by C -; -; Output: -; Result: HL : 16 bit -; Registers Used: -; none -; Comments: -; Created 12/2001: G.Loegel -;------------------------------------------------------------------------- - .def __sshl, __sshl_b - .assume adl=1 - -__sshl_b equ 000244h -__sshl equ 000240h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Shift Left
+; Input:
+; Operand1:
+; BC : 16 bit number of bits to shift
+; Assume B=0 C=shift count
+; Operand2:
+; HL : 16 bit value to be shifted by C
+;
+; Output:
+; Result: HL : 16 bit
+; Registers Used:
+; none
+; Comments:
+; Created 12/2001: G.Loegel
+;-------------------------------------------------------------------------
+ .def __sshl, __sshl_b
+ .assume adl=1
+
+__sshl_b equ 000244h
+__sshl equ 000240h
diff --git a/frontends/calculator/CEdev/lib/shared/sshrs.src b/frontends/calculator/CEdev/lib/shared/sshrs.src index a997ae1..94be572 100644 --- a/frontends/calculator/CEdev/lib/shared/sshrs.src +++ b/frontends/calculator/CEdev/lib/shared/sshrs.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Shift Right Signed -; Input: -; Operand1: -; BC : 16 bit number of bits to shift -; Assume B=0 C=shift count -; Operand2: -; HL : 16 bit value to be shifted by C -; -; Output: -; Result: HL : 16 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __sshrs, __sshrs_b - .assume adl=1 - -__sshrs_b equ 00024Ch -__sshrs equ 000248h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Shift Right Signed
+; Input:
+; Operand1:
+; BC : 16 bit number of bits to shift
+; Assume B=0 C=shift count
+; Operand2:
+; HL : 16 bit value to be shifted by C
+;
+; Output:
+; Result: HL : 16 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __sshrs, __sshrs_b
+ .assume adl=1
+
+__sshrs_b equ 00024Ch
+__sshrs equ 000248h
diff --git a/frontends/calculator/CEdev/lib/shared/sshru.src b/frontends/calculator/CEdev/lib/shared/sshru.src index 796f776..3a47401 100644 --- a/frontends/calculator/CEdev/lib/shared/sshru.src +++ b/frontends/calculator/CEdev/lib/shared/sshru.src @@ -1,20 +1,20 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Short Shift Right Unsigned -; Input: -; Operand1: -; BC : 16 bit number of bits to shift -; Assume B=0 C=shift count -; Operand2: -; HL : 16 bit value to be shifted by C -; -; Output: -; Result: HL : 16 bit -; Registers Used: -; none -;------------------------------------------------------------------------- - .def __sshru, __sshru_b - .assume adl=1 - -__sshru_b equ 000254h -__sshru equ 000250h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Short Shift Right Unsigned
+; Input:
+; Operand1:
+; BC : 16 bit number of bits to shift
+; Assume B=0 C=shift count
+; Operand2:
+; HL : 16 bit value to be shifted by C
+;
+; Output:
+; Result: HL : 16 bit
+; Registers Used:
+; none
+;-------------------------------------------------------------------------
+ .def __sshru, __sshru_b
+ .assume adl=1
+
+__sshru_b equ 000254h
+__sshru equ 000250h
diff --git a/frontends/calculator/CEdev/lib/shared/sstix.src b/frontends/calculator/CEdev/lib/shared/sstix.src index 6f0a11b..652d263 100644 --- a/frontends/calculator/CEdev/lib/shared/sstix.src +++ b/frontends/calculator/CEdev/lib/shared/sstix.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Integer store (ix+nnnnnn),HL -; Input: -; Operand1: -; BC : 24-bit offset from ix -; HL : 16-bit integer to store -; -; Output: -; -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __sstix - .assume adl=1 - -__sstix equ 000258h - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Integer store (ix+nnnnnn),HL
+; Input:
+; Operand1:
+; BC : 24-bit offset from ix
+; HL : 16-bit integer to store
+;
+; Output:
+;
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __sstix
+ .assume adl=1
+
+__sstix equ 000258h
+
diff --git a/frontends/calculator/CEdev/lib/shared/sstiy.src b/frontends/calculator/CEdev/lib/shared/sstiy.src index 504133c..799a899 100644 --- a/frontends/calculator/CEdev/lib/shared/sstiy.src +++ b/frontends/calculator/CEdev/lib/shared/sstiy.src @@ -1,19 +1,19 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; short store (iy+nnnnnn),HL -; Input: -; Operand1: -; BC : 24-bit offset from iy -; HL : 16-bit integer to store -; -; Output: -; -; -; Registers Used: -; -;------------------------------------------------------------------------- - .def __sstiy - .assume adl=1 - -__sstiy equ 00025Ch - +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; short store (iy+nnnnnn),HL
+; Input:
+; Operand1:
+; BC : 24-bit offset from iy
+; HL : 16-bit integer to store
+;
+; Output:
+;
+;
+; Registers Used:
+;
+;-------------------------------------------------------------------------
+ .def __sstiy
+ .assume adl=1
+
+__sstiy equ 00025Ch
+
diff --git a/frontends/calculator/CEdev/lib/shared/stoi.src b/frontends/calculator/CEdev/lib/shared/stoi.src index 9ad6430..e4b66d6 100644 --- a/frontends/calculator/CEdev/lib/shared/stoi.src +++ b/frontends/calculator/CEdev/lib/shared/stoi.src @@ -1,16 +1,16 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Signed Short to Integer Conversion -; Input: -; Operand1: -; BC : 16 bit number to convert -; -; Output: -; Result: HL : 24 bit -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __stoi - .assume adl=1 - -__stoi equ 000260h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Signed Short to Integer Conversion
+; Input:
+; Operand1:
+; BC : 16 bit number to convert
+;
+; Output:
+; Result: HL : 24 bit
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __stoi
+ .assume adl=1
+
+__stoi equ 000260h
diff --git a/frontends/calculator/CEdev/lib/shared/stoiu.src b/frontends/calculator/CEdev/lib/shared/stoiu.src index db0d59e..1985544 100644 --- a/frontends/calculator/CEdev/lib/shared/stoiu.src +++ b/frontends/calculator/CEdev/lib/shared/stoiu.src @@ -1,16 +1,16 @@ -; (c) Copyright 2001-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Unsigned Short to Integer Conversion -; Input: -; Operand1: -; BC : 16 bit number to convert -; -; Output: -; Result: HL : 24 bit -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __stoiu - .assume adl=1 - -__stoiu equ 000264h +; (c) Copyright 2001-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Unsigned Short to Integer Conversion
+; Input:
+; Operand1:
+; BC : 16 bit number to convert
+;
+; Output:
+; Result: HL : 24 bit
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __stoiu
+ .assume adl=1
+
+__stoiu equ 000264h
diff --git a/frontends/calculator/CEdev/lib/shared/strcasecmp.src b/frontends/calculator/CEdev/lib/shared/strcasecmp.src index 2808f5b..abc6b93 100644 --- a/frontends/calculator/CEdev/lib/shared/strcasecmp.src +++ b/frontends/calculator/CEdev/lib/shared/strcasecmp.src @@ -1,6 +1,6 @@ - .def _strcasecmp - .assume adl=1 - -; int strcasecmp(const char *f1, const char *f2); - + .def _strcasecmp
+ .assume adl=1
+
+; int strcasecmp(const char *f1, const char *f2);
+
_strcasecmp equ 021E3Ch
\ No newline at end of file diff --git a/frontends/calculator/CEdev/lib/shared/strcat.src b/frontends/calculator/CEdev/lib/shared/strcat.src index 297e5da..553c111 100644 --- a/frontends/calculator/CEdev/lib/shared/strcat.src +++ b/frontends/calculator/CEdev/lib/shared/strcat.src @@ -1,6 +1,6 @@ - .def _strcat - .assume adl=1 - -; char *strcat(char *s1, char *s2); - -_strcat equ 0000C0h + .def _strcat
+ .assume adl=1
+
+; char *strcat(char *s1, char *s2);
+
+_strcat equ 0000C0h
diff --git a/frontends/calculator/CEdev/lib/shared/strchr.src b/frontends/calculator/CEdev/lib/shared/strchr.src index 103602b..109a37c 100644 --- a/frontends/calculator/CEdev/lib/shared/strchr.src +++ b/frontends/calculator/CEdev/lib/shared/strchr.src @@ -1,6 +1,6 @@ - .def _strchr - .assume adl=1 - -; char *strchr(char *s, int c); - -_strchr equ 0000C4h + .def _strchr
+ .assume adl=1
+
+; char *strchr(char *s, int c);
+
+_strchr equ 0000C4h
diff --git a/frontends/calculator/CEdev/lib/shared/strcmp.src b/frontends/calculator/CEdev/lib/shared/strcmp.src index 9eb4f6e..3ba6280 100644 --- a/frontends/calculator/CEdev/lib/shared/strcmp.src +++ b/frontends/calculator/CEdev/lib/shared/strcmp.src @@ -1,6 +1,6 @@ - .def _strcmp - .assume adl=1 - -; int strcmp(register char *s1, register char *s2) - -_strcmp equ 0000C8h + .def _strcmp
+ .assume adl=1
+
+; int strcmp(register char *s1, register char *s2)
+
+_strcmp equ 0000C8h
diff --git a/frontends/calculator/CEdev/lib/shared/strcpy.src b/frontends/calculator/CEdev/lib/shared/strcpy.src index 38c0eb0..da9a089 100644 --- a/frontends/calculator/CEdev/lib/shared/strcpy.src +++ b/frontends/calculator/CEdev/lib/shared/strcpy.src @@ -1,6 +1,6 @@ - .def _strcpy - .assume adl=1 - -; char *strcpy(void *d, void *s); - -_strcpy equ 0000CCh + .def _strcpy
+ .assume adl=1
+
+; char *strcpy(void *d, void *s);
+
+_strcpy equ 0000CCh
diff --git a/frontends/calculator/CEdev/lib/shared/strcspn.src b/frontends/calculator/CEdev/lib/shared/strcspn.src index 1d83171..ca3d1ff 100644 --- a/frontends/calculator/CEdev/lib/shared/strcspn.src +++ b/frontends/calculator/CEdev/lib/shared/strcspn.src @@ -1,6 +1,6 @@ - .def _strcspn - .assume adl=1 - -; size_t strcspn(char *s1, char *s2); - -_strcspn equ 0000D0h + .def _strcspn
+ .assume adl=1
+
+; size_t strcspn(char *s1, char *s2);
+
+_strcspn equ 0000D0h
diff --git a/frontends/calculator/CEdev/lib/shared/strdup.src b/frontends/calculator/CEdev/lib/shared/strdup.src index 2debaa3..4e893ca 100644 --- a/frontends/calculator/CEdev/lib/shared/strdup.src +++ b/frontends/calculator/CEdev/lib/shared/strdup.src @@ -1,35 +1,35 @@ - .ref __frameset - .ref _malloc - .ref _strlen - .ref _strcpy - .def _strdup - .assume adl=1 - -_strdup: - ld hl,-3 - call __frameset - ld bc,(ix+6) - push bc - call _strlen - pop bc - inc hl - push hl - call _malloc - pop bc - ld (ix+-3),hl - add hl,de - or a,a - sbc hl,de - jr z,MallocFail - ld bc,(ix+6) - push bc - ld bc,(ix+-3) - push bc - call _strcpy - pop bc - pop bc -MallocFail: - ld hl,(ix+-3) - ld sp,ix - pop ix - ret + .ref __frameset
+ .ref _malloc
+ .ref _strlen
+ .ref _strcpy
+ .def _strdup
+ .assume adl=1
+
+_strdup:
+ ld hl,-3
+ call __frameset
+ ld bc,(ix+6)
+ push bc
+ call _strlen
+ pop bc
+ inc hl
+ push hl
+ call _malloc
+ pop bc
+ ld (ix+-3),hl
+ add hl,de
+ or a,a
+ sbc hl,de
+ jr z,MallocFail
+ ld bc,(ix+6)
+ push bc
+ ld bc,(ix+-3)
+ push bc
+ call _strcpy
+ pop bc
+ pop bc
+MallocFail:
+ ld hl,(ix+-3)
+ ld sp,ix
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/strlen.src b/frontends/calculator/CEdev/lib/shared/strlen.src index 5ef9fad..12abdfc 100644 --- a/frontends/calculator/CEdev/lib/shared/strlen.src +++ b/frontends/calculator/CEdev/lib/shared/strlen.src @@ -1,6 +1,6 @@ - .def _strlen - .assume adl=1 - -; size_t strlen(char *s); - -_strlen equ 0000D4h + .def _strlen
+ .assume adl=1
+
+; size_t strlen(char *s);
+
+_strlen equ 0000D4h
diff --git a/frontends/calculator/CEdev/lib/shared/strncasecmp.src b/frontends/calculator/CEdev/lib/shared/strncasecmp.src index fdc603e..2e0dc4b 100644 --- a/frontends/calculator/CEdev/lib/shared/strncasecmp.src +++ b/frontends/calculator/CEdev/lib/shared/strncasecmp.src @@ -1,6 +1,6 @@ - .def _strncasecmp - .assume adl=1 - -; int strncasecmp ( const char *str1 , const char *str2 , int len ); - -_strncasecmp equ 021E3Ch + .def _strncasecmp
+ .assume adl=1
+
+; int strncasecmp ( const char *str1 , const char *str2 , int len );
+
+_strncasecmp equ 021E3Ch
diff --git a/frontends/calculator/CEdev/lib/shared/strncat.src b/frontends/calculator/CEdev/lib/shared/strncat.src index 5f6a532..9d7e8be 100644 --- a/frontends/calculator/CEdev/lib/shared/strncat.src +++ b/frontends/calculator/CEdev/lib/shared/strncat.src @@ -1,6 +1,6 @@ - .def _strncat - .assume adl=1 - -; char *strncat(char *s1, char *s2, size_t n) - -_strncat equ 0000D8h + .def _strncat
+ .assume adl=1
+
+; char *strncat(char *s1, char *s2, size_t n)
+
+_strncat equ 0000D8h
diff --git a/frontends/calculator/CEdev/lib/shared/strncmp.src b/frontends/calculator/CEdev/lib/shared/strncmp.src index 08f2750..62bc058 100644 --- a/frontends/calculator/CEdev/lib/shared/strncmp.src +++ b/frontends/calculator/CEdev/lib/shared/strncmp.src @@ -1,6 +1,6 @@ - .def _strncmp - .assume adl=1 - -; int strncmp(char *s1, char *s2, size_t n) - -_strncmp equ 0000DCh + .def _strncmp
+ .assume adl=1
+
+; int strncmp(char *s1, char *s2, size_t n)
+
+_strncmp equ 0000DCh
diff --git a/frontends/calculator/CEdev/lib/shared/strncpy.src b/frontends/calculator/CEdev/lib/shared/strncpy.src index b46a72e..ef359b2 100644 --- a/frontends/calculator/CEdev/lib/shared/strncpy.src +++ b/frontends/calculator/CEdev/lib/shared/strncpy.src @@ -1,6 +1,6 @@ - .def _strncpy - .assume adl=1 - -; char *strncpy(char *dst, char *src, size_t n) - -_strncpy equ 0000E0h + .def _strncpy
+ .assume adl=1
+
+; char *strncpy(char *dst, char *src, size_t n)
+
+_strncpy equ 0000E0h
diff --git a/frontends/calculator/CEdev/lib/shared/strndup.src b/frontends/calculator/CEdev/lib/shared/strndup.src index 26c656c..b2ee007 100644 --- a/frontends/calculator/CEdev/lib/shared/strndup.src +++ b/frontends/calculator/CEdev/lib/shared/strndup.src @@ -1,46 +1,46 @@ - .def _strndup - .ref __frameset - .ref _strlen - .ref _malloc - .ref _memcpy - .assume adl=1 - -_strndup: - ld hl,-6 - call __frameset - ld bc,(ix+6) - push bc - call _strlen - ld (ix+-3),hl - ex de,hl - ld hl,(ix+9) - or a,a - sbc hl,de - jr nc,Greater - ld hl,(ix+9) - ld (ix+-3),hl -Greater: - ld bc,(ix+-3) - inc bc - push bc - call _malloc - ld (ix+-6),hl - add hl,bc - or a,a - sbc hl,bc - jr z,MallocFail - ld bc,(ix+-3) - ld hl,(ix+-6) - add hl,bc - ld (hl),0 - or a,a - sbc hl,bc - push bc - ld bc,(ix+6) - push bc - push hl - call _memcpy -MallocFail: - ld sp,ix - pop ix - ret + .def _strndup
+ .ref __frameset
+ .ref _strlen
+ .ref _malloc
+ .ref _memcpy
+ .assume adl=1
+
+_strndup:
+ ld hl,-6
+ call __frameset
+ ld bc,(ix+6)
+ push bc
+ call _strlen
+ ld (ix+-3),hl
+ ex de,hl
+ ld hl,(ix+9)
+ or a,a
+ sbc hl,de
+ jr nc,Greater
+ ld hl,(ix+9)
+ ld (ix+-3),hl
+Greater:
+ ld bc,(ix+-3)
+ inc bc
+ push bc
+ call _malloc
+ ld (ix+-6),hl
+ add hl,bc
+ or a,a
+ sbc hl,bc
+ jr z,MallocFail
+ ld bc,(ix+-3)
+ ld hl,(ix+-6)
+ add hl,bc
+ ld (hl),0
+ or a,a
+ sbc hl,bc
+ push bc
+ ld bc,(ix+6)
+ push bc
+ push hl
+ call _memcpy
+MallocFail:
+ ld sp,ix
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/strnlen.src b/frontends/calculator/CEdev/lib/shared/strnlen.src index 823ea49..f7e7380 100644 --- a/frontends/calculator/CEdev/lib/shared/strnlen.src +++ b/frontends/calculator/CEdev/lib/shared/strnlen.src @@ -1,27 +1,27 @@ - .def _strnlen - .ref __frameset0 - .assume adl=1 - -_strnlen: - call __frameset0 - ld de,(ix+6) - ld bc,(ix+9) - or a,a - sbc hl,hl - jr StartFor -ForLoop: - inc hl - inc de -StartFor: - push hl - or a,a - sbc hl,bc - pop hl - jr nc,ReachedMax - ld a,(de) - or a,a - jr nz,ForLoop -ReachedMax: - ld sp,ix - pop ix - ret + .def _strnlen
+ .ref __frameset0
+ .assume adl=1
+
+_strnlen:
+ call __frameset0
+ ld de,(ix+6)
+ ld bc,(ix+9)
+ or a,a
+ sbc hl,hl
+ jr StartFor
+ForLoop:
+ inc hl
+ inc de
+StartFor:
+ push hl
+ or a,a
+ sbc hl,bc
+ pop hl
+ jr nc,ReachedMax
+ ld a,(de)
+ or a,a
+ jr nz,ForLoop
+ReachedMax:
+ ld sp,ix
+ pop ix
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/strpbrk.src b/frontends/calculator/CEdev/lib/shared/strpbrk.src index f9ff01f..ee38418 100644 --- a/frontends/calculator/CEdev/lib/shared/strpbrk.src +++ b/frontends/calculator/CEdev/lib/shared/strpbrk.src @@ -1,6 +1,6 @@ - .def _strpbrk - .assume adl=1 - -; char *strpbrk(char *s1, char *s2) - -_strpbrk equ 0000E4h + .def _strpbrk
+ .assume adl=1
+
+; char *strpbrk(char *s1, char *s2)
+
+_strpbrk equ 0000E4h
diff --git a/frontends/calculator/CEdev/lib/shared/strrchr.src b/frontends/calculator/CEdev/lib/shared/strrchr.src index 80fab4a..d682fa2 100644 --- a/frontends/calculator/CEdev/lib/shared/strrchr.src +++ b/frontends/calculator/CEdev/lib/shared/strrchr.src @@ -1,6 +1,6 @@ - .def _strrchr - .assume adl=1 - -; char *strrchr(char *s, int c) - -_strrchr equ 0000E8h + .def _strrchr
+ .assume adl=1
+
+; char *strrchr(char *s, int c)
+
+_strrchr equ 0000E8h
diff --git a/frontends/calculator/CEdev/lib/shared/strspn.src b/frontends/calculator/CEdev/lib/shared/strspn.src index bb5ad3e..37613d1 100644 --- a/frontends/calculator/CEdev/lib/shared/strspn.src +++ b/frontends/calculator/CEdev/lib/shared/strspn.src @@ -1,5 +1,5 @@ - .def _strspn - .assume adl=1 - -; size_t strspn(char *s1,char *s2) -_strspn equ 0000ECh + .def _strspn
+ .assume adl=1
+
+; size_t strspn(char *s1,char *s2)
+_strspn equ 0000ECh
diff --git a/frontends/calculator/CEdev/lib/shared/strstr.src b/frontends/calculator/CEdev/lib/shared/strstr.src index 585c5c0..a28c80e 100644 --- a/frontends/calculator/CEdev/lib/shared/strstr.src +++ b/frontends/calculator/CEdev/lib/shared/strstr.src @@ -1,6 +1,6 @@ - .def _strstr - .assume adl=1 - -; char *strstr(char *s1, char *s2); - -_strstr equ 0000F0h + .def _strstr
+ .assume adl=1
+
+; char *strstr(char *s1, char *s2);
+
+_strstr equ 0000F0h
diff --git a/frontends/calculator/CEdev/lib/shared/strtok.src b/frontends/calculator/CEdev/lib/shared/strtok.src index 14f3ef6..0bce87d 100644 --- a/frontends/calculator/CEdev/lib/shared/strtok.src +++ b/frontends/calculator/CEdev/lib/shared/strtok.src @@ -1,5 +1,5 @@ - .def _strtok - .assume adl=1 - -_strtok equ 0000F4h + .def _strtok
+ .assume adl=1
+
+_strtok equ 0000F4h
\ No newline at end of file diff --git a/frontends/calculator/CEdev/lib/shared/sxor.src b/frontends/calculator/CEdev/lib/shared/sxor.src index 2771ff2..f6e9ae8 100644 --- a/frontends/calculator/CEdev/lib/shared/sxor.src +++ b/frontends/calculator/CEdev/lib/shared/sxor.src @@ -1,18 +1,18 @@ -;------------------------------------------------------------------------- -; Short XOR. -; Input: -; Operand1: -; bc : 16 bit -; -; Operand2: -; hl : 16 bit -; -; Output: -; Result: hl : 16 bit -; Registers Used: -; a -;------------------------------------------------------------------------- - .def __sxor - .assume adl=1 - -__sxor equ 000268h +;-------------------------------------------------------------------------
+; Short XOR.
+; Input:
+; Operand1:
+; bc : 16 bit
+;
+; Operand2:
+; hl : 16 bit
+;
+; Output:
+; Result: hl : 16 bit
+; Registers Used:
+; a
+;-------------------------------------------------------------------------
+ .def __sxor
+ .assume adl=1
+
+__sxor equ 000268h
diff --git a/frontends/calculator/CEdev/lib/shared/tice.src b/frontends/calculator/CEdev/lib/shared/tice.src index 5467be1..c95ade8 100644 --- a/frontends/calculator/CEdev/lib/shared/tice.src +++ b/frontends/calculator/CEdev/lib/shared/tice.src @@ -1,241 +1,241 @@ -; --- -; external definitions -; --- - .def _boot_GetBootMajorVer - .def _boot_GetHardwareVer - .def _boot_GetBootMinorVer - .def _boot_DebugPrintf - .def _boot_ClearVRAM - .def _boot_TurnOff - .def _boot_NewLine - .def _boot_Set6MHzMode - .def _boot_Set48MHzMode - .def _boot_Set6MHzModeI - .def _boot_Set48MHzModeI - .def _boot_GetBatteryStatus - .def _boot_WaitShort - .def _boot_CheckOnPressed - .def _boot_SetDate - .def _boot_GetDate - .def _boot_GetTime - .def _boot_SetTime - .def _boot_IsAfterNoon - - .def _os_NewLine - .def _os_PushErrorHandler - .def _os_PopErrorHandler - .def _os_ThrowError - .def _os_RealCopy - .def _os_RealAsinRad - .def _os_RealAcosRad - .def _os_RealAtanRad - .def _os_RealAdd - .def _os_CplxSquare - .def _os_RealCompare - .def _os_RealCosRad - .def _os_RealRadToDeg - .def _os_RealDiv - .def _os_RealExp - .def _os_RealFloor - .def _os_RealToStr - .def _os_RealFrac - .def _os_RealGcd - .def _os_RealRoundInt - .def _os_RealLcm - .def _os_RealLog - .def _os_RealMax - .def _os_RealMin - .def _os_RealMul - .def _os_RealNcr - .def _os_RealNeg - .def _os_RealNpr - .def _os_RealPow - .def _os_RealDegToRad - .def _os_RealRandInt - .def _os_RealInv - .def _os_RealMod - .def _os_RealRound - .def _os_RealSinRad - .def _os_RealSqrt - .def _os_RealSub - .def _os_RealTanRad - .def _os_StrToReal - .def _os_RealInt - .def _os_SetFlagBits - .def _os_ResetFlagBits - .def _os_TestFlagBits - .def _os_SetFlagByte - .def _os_GetFlagByte - .def _os_GetCursorPos - .def _os_PutStrFull - .def _os_PutStrLine - .def _os_SetCursorPos - .def _os_AppInit - .def _os_GetKey - .def _os_GetCSC - .def _os_DisableCursor - .def _os_EnableCursor - .def _os_FontDrawText - .def _os_FontGetHeight - .def _os_FontGetWidth - .def _os_InitDrawing - .def _os_SetDrawBGColor - .def _os_SetDrawFGColor - .def _os_FontSelect - .def _os_RclAns - .def _os_SetTimer1 - .def _os_DisableTimer1 - .def _os_GetSystemStats - .def _os_GetDrawBGColor - .def _os_GetDrawFGColor - .def _os_FontGetID - .def _os_RealToInt24 - .def _os_Int24ToReal - .def _os_ForceCmdNoChar - .def _os_GetSymTablePtr - .def _os_NextSymEntry - .def _os_ChkFindSym - .def _os_MemChk - .def _os_SetTimer2 - .def _os_DisableTimer2 - .def _os_FloatToReal - .def _os_RealToFloat - .def _os_FontDrawTransText - .def _os_CreateAppVar - - .def _asm_MoveDown - .def _asm_MoveUp - .def _asm_ClrLCDFull - .def _asm_ClrLCD - .def _asm_ClrTxtShd - .def _asm_HomeUp - .def _asm_RunIndicOn - .def _asm_RunIndicOff - .def _asm_DelRes - .def _asm_DisableAPD - .def _asm_EnableAPD - .def _asm_DrawStatusBar - .def _asm_ArcChk - .assume adl=1 - -; --- -; locations -; --- -_boot_GetBootMajorVer equ 000080h -_boot_GetHardwareVer equ 000084h -_boot_GetBootMinorVer equ 00008Ch -_boot_DebugPrintf equ 0000B4h -_boot_ClearVRAM equ 000374h -_boot_TurnOff equ 000388h -_boot_NewLine equ 000390h -_boot_Set6MHzMode equ 00039Ch -_boot_Set48MHzMode equ 0003A0h -_boot_Set6MHzModeI equ 0003A4h -_boot_Set48MHzModeI equ 0003A8h -_boot_GetBatteryStatus equ 0003B0h -_boot_WaitShort equ 0003B4h -_boot_CheckOnPressed equ 00057Ch -_boot_SetDate equ 000598h -_boot_GetDate equ 0005A8h -_boot_GetTime equ 0005B0h -_boot_SetTime equ 0005B4h -_boot_IsAfterNoon equ 0005C8h - -_os_NewLine equ 0207F0h -_os_PushErrorHandler equ 021C78h -_os_PopErrorHandler equ 021C7Ch -_os_ThrowError equ 021C80h -_os_RealCopy equ 021C84h -_os_RealAsinRad equ 021C88h -_os_RealAcosRad equ 021C8Ch -_os_RealAtanRad equ 021C90h -_os_RealAdd equ 021C94h -_os_CplxSquare equ 021C98h -_os_RealCompare equ 021C9Ch -_os_RealCosRad equ 021CA0h -_os_RealRadToDeg equ 021CA4h -_os_RealDiv equ 021CA8h -_os_RealExp equ 021CACh -_os_RealFloor equ 021CB0h -_os_RealToStr equ 021CB4h -_os_RealFrac equ 021CB8h -_os_RealGcd equ 021CBCh -_os_RealRoundInt equ 021CC0h -_os_RealLcm equ 021CC4h -_os_RealLog equ 021CC8h -_os_RealMax equ 021CCCh -_os_RealMin equ 021CD0h -_os_RealMul equ 021CD4h -_os_RealNcr equ 021CD8h -_os_RealNeg equ 021CDCh -_os_RealNpr equ 021CE0h -_os_RealPow equ 021CE4h -_os_RealDegToRad equ 021CE8h -_os_RealRandInt equ 021CECh -_os_RealInv equ 021CF0h -_os_RealMod equ 021CF4h -_os_RealRound equ 021CF8h -_os_RealSinRad equ 021CFCh -_os_RealSqrt equ 021D00h -_os_RealSub equ 021D04h -_os_RealTanRad equ 021D08h -_os_StrToReal equ 021D0Ch -_os_RealInt equ 021D10h -_os_SetFlagBits equ 021D14h -_os_ResetFlagBits equ 021D18h -_os_TestFlagBits equ 021D1Ch -_os_SetFlagByte equ 021D20h -_os_GetFlagByte equ 021D24h -_os_GetCursorPos equ 021D28h -_os_PutStrFull equ 021D2Ch -_os_PutStrLine equ 021D30h -_os_SetCursorPos equ 021D34h -_os_AppInit equ 021D40h -_os_GetKey equ 021D38h -_os_GetCSC equ 021D3Ch -_os_DisableCursor equ 021DE4h -_os_EnableCursor equ 021DE8h -_os_FontDrawText equ 021E00h -_os_FontGetHeight equ 021E14h -_os_FontGetWidth equ 021E18h -_os_InitDrawing equ 021E1Ch -_os_SetDrawBGColor equ 021E20h -_os_SetDrawFGColor equ 021E24h -_os_FontSelect equ 021E28h -_os_RclAns equ 021E70h -_os_SetTimer1 equ 021EC8h -_os_DisableTimer1 equ 021ECCh -_os_GetSystemStats equ 021ED4h -_os_GetDrawBGColor equ 021EE4h -_os_GetDrawFGColor equ 021EE8h -_os_FontGetID equ 021EECh -_os_RealToInt24 equ 021EF4h -_os_Int24ToReal equ 021EF8h -_os_ForceCmdNoChar equ 021FA8h -_os_GetSymTablePtr equ 021FB0h -_os_NextSymEntry equ 021FB4h -_os_ChkFindSym equ 021FB8h -_os_MemChk equ 021FF0h -_os_SetTimer2 equ 022080h -_os_DisableTimer2 equ 022084h -_os_FloatToReal equ 022170h -_os_RealToFloat equ 022174h -_os_FontDrawTransText equ 022178h -_os_CreateAppVar equ 022184h - -; --- -; directly callable asm functions -; --- -_asm_MoveDown equ 0207F4h -_asm_MoveUp equ 020800h -_asm_ClrLCDFull equ 020808h -_asm_ClrLCD equ 02080Ch -_asm_ClrTxtShd equ 020818h -_asm_HomeUp equ 020828h -_asm_RunIndicOn equ 020844h -_asm_RunIndicOff equ 020848h -_asm_DelRes equ 020E5Ch -_asm_DisableAPD equ 021134h -_asm_EnableAPD equ 021138h -_asm_DrawStatusBar equ 021A3Ch -_asm_ArcChk equ 022040h +; ---
+; external definitions
+; ---
+ .def _boot_GetBootMajorVer
+ .def _boot_GetHardwareVer
+ .def _boot_GetBootMinorVer
+ .def _boot_DebugPrintf
+ .def _boot_ClearVRAM
+ .def _boot_TurnOff
+ .def _boot_NewLine
+ .def _boot_Set6MHzMode
+ .def _boot_Set48MHzMode
+ .def _boot_Set6MHzModeI
+ .def _boot_Set48MHzModeI
+ .def _boot_GetBatteryStatus
+ .def _boot_WaitShort
+ .def _boot_CheckOnPressed
+ .def _boot_SetDate
+ .def _boot_GetDate
+ .def _boot_GetTime
+ .def _boot_SetTime
+ .def _boot_IsAfterNoon
+
+ .def _os_NewLine
+ .def _os_PushErrorHandler
+ .def _os_PopErrorHandler
+ .def _os_ThrowError
+ .def _os_RealCopy
+ .def _os_RealAsinRad
+ .def _os_RealAcosRad
+ .def _os_RealAtanRad
+ .def _os_RealAdd
+ .def _os_CplxSquare
+ .def _os_RealCompare
+ .def _os_RealCosRad
+ .def _os_RealRadToDeg
+ .def _os_RealDiv
+ .def _os_RealExp
+ .def _os_RealFloor
+ .def _os_RealToStr
+ .def _os_RealFrac
+ .def _os_RealGcd
+ .def _os_RealRoundInt
+ .def _os_RealLcm
+ .def _os_RealLog
+ .def _os_RealMax
+ .def _os_RealMin
+ .def _os_RealMul
+ .def _os_RealNcr
+ .def _os_RealNeg
+ .def _os_RealNpr
+ .def _os_RealPow
+ .def _os_RealDegToRad
+ .def _os_RealRandInt
+ .def _os_RealInv
+ .def _os_RealMod
+ .def _os_RealRound
+ .def _os_RealSinRad
+ .def _os_RealSqrt
+ .def _os_RealSub
+ .def _os_RealTanRad
+ .def _os_StrToReal
+ .def _os_RealInt
+ .def _os_SetFlagBits
+ .def _os_ResetFlagBits
+ .def _os_TestFlagBits
+ .def _os_SetFlagByte
+ .def _os_GetFlagByte
+ .def _os_GetCursorPos
+ .def _os_PutStrFull
+ .def _os_PutStrLine
+ .def _os_SetCursorPos
+ .def _os_AppInit
+ .def _os_GetKey
+ .def _os_GetCSC
+ .def _os_DisableCursor
+ .def _os_EnableCursor
+ .def _os_FontDrawText
+ .def _os_FontGetHeight
+ .def _os_FontGetWidth
+ .def _os_InitDrawing
+ .def _os_SetDrawBGColor
+ .def _os_SetDrawFGColor
+ .def _os_FontSelect
+ .def _os_RclAns
+ .def _os_SetTimer1
+ .def _os_DisableTimer1
+ .def _os_GetSystemStats
+ .def _os_GetDrawBGColor
+ .def _os_GetDrawFGColor
+ .def _os_FontGetID
+ .def _os_RealToInt24
+ .def _os_Int24ToReal
+ .def _os_ForceCmdNoChar
+ .def _os_GetSymTablePtr
+ .def _os_NextSymEntry
+ .def _os_ChkFindSym
+ .def _os_MemChk
+ .def _os_SetTimer2
+ .def _os_DisableTimer2
+ .def _os_FloatToReal
+ .def _os_RealToFloat
+ .def _os_FontDrawTransText
+ .def _os_CreateAppVar
+
+ .def _asm_MoveDown
+ .def _asm_MoveUp
+ .def _asm_ClrLCDFull
+ .def _asm_ClrLCD
+ .def _asm_ClrTxtShd
+ .def _asm_HomeUp
+ .def _asm_RunIndicOn
+ .def _asm_RunIndicOff
+ .def _asm_DelRes
+ .def _asm_DisableAPD
+ .def _asm_EnableAPD
+ .def _asm_DrawStatusBar
+ .def _asm_ArcChk
+ .assume adl=1
+
+; ---
+; locations
+; ---
+_boot_GetBootMajorVer equ 000080h
+_boot_GetHardwareVer equ 000084h
+_boot_GetBootMinorVer equ 00008Ch
+_boot_DebugPrintf equ 0000B4h
+_boot_ClearVRAM equ 000374h
+_boot_TurnOff equ 000388h
+_boot_NewLine equ 000390h
+_boot_Set6MHzMode equ 00039Ch
+_boot_Set48MHzMode equ 0003A0h
+_boot_Set6MHzModeI equ 0003A4h
+_boot_Set48MHzModeI equ 0003A8h
+_boot_GetBatteryStatus equ 0003B0h
+_boot_WaitShort equ 0003B4h
+_boot_CheckOnPressed equ 00057Ch
+_boot_SetDate equ 000598h
+_boot_GetDate equ 0005A8h
+_boot_GetTime equ 0005B0h
+_boot_SetTime equ 0005B4h
+_boot_IsAfterNoon equ 0005C8h
+
+_os_NewLine equ 0207F0h
+_os_PushErrorHandler equ 021C78h
+_os_PopErrorHandler equ 021C7Ch
+_os_ThrowError equ 021C80h
+_os_RealCopy equ 021C84h
+_os_RealAsinRad equ 021C88h
+_os_RealAcosRad equ 021C8Ch
+_os_RealAtanRad equ 021C90h
+_os_RealAdd equ 021C94h
+_os_CplxSquare equ 021C98h
+_os_RealCompare equ 021C9Ch
+_os_RealCosRad equ 021CA0h
+_os_RealRadToDeg equ 021CA4h
+_os_RealDiv equ 021CA8h
+_os_RealExp equ 021CACh
+_os_RealFloor equ 021CB0h
+_os_RealToStr equ 021CB4h
+_os_RealFrac equ 021CB8h
+_os_RealGcd equ 021CBCh
+_os_RealRoundInt equ 021CC0h
+_os_RealLcm equ 021CC4h
+_os_RealLog equ 021CC8h
+_os_RealMax equ 021CCCh
+_os_RealMin equ 021CD0h
+_os_RealMul equ 021CD4h
+_os_RealNcr equ 021CD8h
+_os_RealNeg equ 021CDCh
+_os_RealNpr equ 021CE0h
+_os_RealPow equ 021CE4h
+_os_RealDegToRad equ 021CE8h
+_os_RealRandInt equ 021CECh
+_os_RealInv equ 021CF0h
+_os_RealMod equ 021CF4h
+_os_RealRound equ 021CF8h
+_os_RealSinRad equ 021CFCh
+_os_RealSqrt equ 021D00h
+_os_RealSub equ 021D04h
+_os_RealTanRad equ 021D08h
+_os_StrToReal equ 021D0Ch
+_os_RealInt equ 021D10h
+_os_SetFlagBits equ 021D14h
+_os_ResetFlagBits equ 021D18h
+_os_TestFlagBits equ 021D1Ch
+_os_SetFlagByte equ 021D20h
+_os_GetFlagByte equ 021D24h
+_os_GetCursorPos equ 021D28h
+_os_PutStrFull equ 021D2Ch
+_os_PutStrLine equ 021D30h
+_os_SetCursorPos equ 021D34h
+_os_AppInit equ 021D40h
+_os_GetKey equ 021D38h
+_os_GetCSC equ 021D3Ch
+_os_DisableCursor equ 021DE4h
+_os_EnableCursor equ 021DE8h
+_os_FontDrawText equ 021E00h
+_os_FontGetHeight equ 021E14h
+_os_FontGetWidth equ 021E18h
+_os_InitDrawing equ 021E1Ch
+_os_SetDrawBGColor equ 021E20h
+_os_SetDrawFGColor equ 021E24h
+_os_FontSelect equ 021E28h
+_os_RclAns equ 021E70h
+_os_SetTimer1 equ 021EC8h
+_os_DisableTimer1 equ 021ECCh
+_os_GetSystemStats equ 021ED4h
+_os_GetDrawBGColor equ 021EE4h
+_os_GetDrawFGColor equ 021EE8h
+_os_FontGetID equ 021EECh
+_os_RealToInt24 equ 021EF4h
+_os_Int24ToReal equ 021EF8h
+_os_ForceCmdNoChar equ 021FA8h
+_os_GetSymTablePtr equ 021FB0h
+_os_NextSymEntry equ 021FB4h
+_os_ChkFindSym equ 021FB8h
+_os_MemChk equ 021FF0h
+_os_SetTimer2 equ 022080h
+_os_DisableTimer2 equ 022084h
+_os_FloatToReal equ 022170h
+_os_RealToFloat equ 022174h
+_os_FontDrawTransText equ 022178h
+_os_CreateAppVar equ 022184h
+
+; ---
+; directly callable asm functions
+; ---
+_asm_MoveDown equ 0207F4h
+_asm_MoveUp equ 020800h
+_asm_ClrLCDFull equ 020808h
+_asm_ClrLCD equ 02080Ch
+_asm_ClrTxtShd equ 020818h
+_asm_HomeUp equ 020828h
+_asm_RunIndicOn equ 020844h
+_asm_RunIndicOff equ 020848h
+_asm_DelRes equ 020E5Ch
+_asm_DisableAPD equ 021134h
+_asm_EnableAPD equ 021138h
+_asm_DrawStatusBar equ 021A3Ch
+_asm_ArcChk equ 022040h
diff --git a/frontends/calculator/CEdev/lib/shared/tolower.src b/frontends/calculator/CEdev/lib/shared/tolower.src index db6c58d..a389331 100644 --- a/frontends/calculator/CEdev/lib/shared/tolower.src +++ b/frontends/calculator/CEdev/lib/shared/tolower.src @@ -1,4 +1,4 @@ - .assume adl=1 - .def _tolower - -_tolower equ 021E34h + .assume adl=1
+ .def _tolower
+
+_tolower equ 021E34h
diff --git a/frontends/calculator/CEdev/lib/shared/toupper.src b/frontends/calculator/CEdev/lib/shared/toupper.src index eb5dcea..9edc2b1 100644 --- a/frontends/calculator/CEdev/lib/shared/toupper.src +++ b/frontends/calculator/CEdev/lib/shared/toupper.src @@ -1,4 +1,4 @@ - .assume adl=1 - .def _toupper - -_toupper equ 021E38h + .assume adl=1
+ .def _toupper
+
+_toupper equ 021E38h
diff --git a/frontends/calculator/CEdev/lib/shared/uldiv.src b/frontends/calculator/CEdev/lib/shared/uldiv.src index 6acdeac..ff407ac 100644 --- a/frontends/calculator/CEdev/lib/shared/uldiv.src +++ b/frontends/calculator/CEdev/lib/shared/uldiv.src @@ -1,128 +1,128 @@ -; (c) Copyright 1999-2008 Zilog, Inc. -;------------------------------------------------------------------------- -; Unsigned Long Division. -; Input: -; Operand1: -; (ix+9) : high word,high byte -; (ix+8) : high word,low byte -; (ix+7) : low word,high byte -; (ix+6) : low word,low byte -; -; Operand2: -; (ix+15) : high word,high byte -; (ix+14) : high word,low byte -; (ix+13) : low word,high byte -; (ix+12) : low word,low byte -; -; Output: -; Result: b : high byte -; de : low byte -; Registers Used: -; a,b,c,d,e,h,l,iy -;------------------------------------------------------------------------- - .assume adl=1 - .def .uldiv - -.uldiv: - push ix - ld ix,0 - add ix,sp - - ld de,0 ;res = 0; - ld b,0 - - ld hl,0 ;num = 0 - ld c,0 - - ld iy,32 ;i = 32; - -loop: - ;res = res << 1 - ex de,hl - add hl,hl - ld a,b - adc a,b - ld b,a - ex de,hl - - ;num = num << 1 - add hl,hl - ld a,c - adc a,c - ld c,a - - ;x = x << 1 - ld a,(ix+6) - add a,(ix+6) - ld (ix+6),a - ld a,(ix+7) - adc a,(ix+7) - ld (ix+7),a - ld a,(ix+8) - adc a,(ix+8) - ld (ix+8),a - ld a,(ix+9) - adc a,(ix+9) - ld (ix+9),a - - - push de - - ;num = num + carry - - ld de,0 - adc hl,de - ld a,c - adc a,d - ld c,a - - - ;num = num - y - ld de,(ix+12) - or a,a - sbc hl,de - ld a,c - ld d,(ix+15) - sbc a,d - ld c,a - - pop de - jr c, out ;if (num < y) goto out - - inc de ;res = res | 1 - - jr done ;goto done - -out: - push de - ;num = num + y - ld de,(ix+12) - add hl,de - ld a,c - ld d,(ix+15) - adc a,d - ld c,a - - pop de - -done: - ;i--, if (i != 0) go to loop - dec iyl - jr nz,loop - - - pop ix - ret - - .def .uldivbdechl -.uldivbdechl: - push bc - push hl - ld c,b - push bc - push de - call .uldiv - ld iy,12 - add iy,sp - ld sp,iy - ret +; (c) Copyright 1999-2008 Zilog, Inc.
+;-------------------------------------------------------------------------
+; Unsigned Long Division.
+; Input:
+; Operand1:
+; (ix+9) : high word,high byte
+; (ix+8) : high word,low byte
+; (ix+7) : low word,high byte
+; (ix+6) : low word,low byte
+;
+; Operand2:
+; (ix+15) : high word,high byte
+; (ix+14) : high word,low byte
+; (ix+13) : low word,high byte
+; (ix+12) : low word,low byte
+;
+; Output:
+; Result: b : high byte
+; de : low byte
+; Registers Used:
+; a,b,c,d,e,h,l,iy
+;-------------------------------------------------------------------------
+ .assume adl=1
+ .def .uldiv
+
+.uldiv:
+ push ix
+ ld ix,0
+ add ix,sp
+
+ ld de,0 ;res = 0;
+ ld b,0
+
+ ld hl,0 ;num = 0
+ ld c,0
+
+ ld iy,32 ;i = 32;
+
+loop:
+ ;res = res << 1
+ ex de,hl
+ add hl,hl
+ ld a,b
+ adc a,b
+ ld b,a
+ ex de,hl
+
+ ;num = num << 1
+ add hl,hl
+ ld a,c
+ adc a,c
+ ld c,a
+
+ ;x = x << 1
+ ld a,(ix+6)
+ add a,(ix+6)
+ ld (ix+6),a
+ ld a,(ix+7)
+ adc a,(ix+7)
+ ld (ix+7),a
+ ld a,(ix+8)
+ adc a,(ix+8)
+ ld (ix+8),a
+ ld a,(ix+9)
+ adc a,(ix+9)
+ ld (ix+9),a
+
+
+ push de
+
+ ;num = num + carry
+
+ ld de,0
+ adc hl,de
+ ld a,c
+ adc a,d
+ ld c,a
+
+
+ ;num = num - y
+ ld de,(ix+12)
+ or a,a
+ sbc hl,de
+ ld a,c
+ ld d,(ix+15)
+ sbc a,d
+ ld c,a
+
+ pop de
+ jr c, out ;if (num < y) goto out
+
+ inc de ;res = res | 1
+
+ jr done ;goto done
+
+out:
+ push de
+ ;num = num + y
+ ld de,(ix+12)
+ add hl,de
+ ld a,c
+ ld d,(ix+15)
+ adc a,d
+ ld c,a
+
+ pop de
+
+done:
+ ;i--, if (i != 0) go to loop
+ dec iyl
+ jr nz,loop
+
+
+ pop ix
+ ret
+
+ .def .uldivbdechl
+.uldivbdechl:
+ push bc
+ push hl
+ ld c,b
+ push bc
+ push de
+ call .uldiv
+ ld iy,12
+ add iy,sp
+ ld sp,iy
+ ret
diff --git a/frontends/calculator/CEdev/lib/shared/usb.src b/frontends/calculator/CEdev/lib/shared/usb.src index 91cc310..f339be8 100644 --- a/frontends/calculator/CEdev/lib/shared/usb.src +++ b/frontends/calculator/CEdev/lib/shared/usb.src @@ -1,21 +1,21 @@ -; --- -; External Definitions -; --- - .def _usb_BusPowered - .def _usb_SelfPowered - .def _usb_ResetChip - .def _usb_DisableTimers - .def _usb_EnableTimers - .def _usb_ResetTimers - .assume adl=1 - -; --- -; Location Equates -; --- -_usb_BusPowered equ 0003E4h -_usb_SelfPowered equ 0003E8h -_usb_ResetChip equ 0003F4h -_usb_DisableTimers equ 0004F4h -_usb_EnableTimers equ 0004F8h -_usb_ResetTimers equ 0004F0h -; --- +; ---
+; External Definitions
+; ---
+ .def _usb_BusPowered
+ .def _usb_SelfPowered
+ .def _usb_ResetChip
+ .def _usb_DisableTimers
+ .def _usb_EnableTimers
+ .def _usb_ResetTimers
+ .assume adl=1
+
+; ---
+; Location Equates
+; ---
+_usb_BusPowered equ 0003E4h
+_usb_SelfPowered equ 0003E8h
+_usb_ResetChip equ 0003F4h
+_usb_DisableTimers equ 0004F4h
+_usb_EnableTimers equ 0004F8h
+_usb_ResetTimers equ 0004F0h
+; ---
diff --git a/frontends/calculator/CEdev/lib/shared/zx7_Decompress.src b/frontends/calculator/CEdev/lib/shared/zx7_Decompress.src index e45c146..3190bdb 100644 --- a/frontends/calculator/CEdev/lib/shared/zx7_Decompress.src +++ b/frontends/calculator/CEdev/lib/shared/zx7_Decompress.src @@ -1,117 +1,117 @@ -; --- -; void zx7_Decompress(void *dest, void *src) -; --- -; Dec 2012 by Einar Saukas & Urusergi -; "Turbo" version (89 bytes, 25% faster) -; --- - - .def _zx7_Decompress - .assume adl=1 - -; enter : hl = void *src -; de = void *dst -; -; exit : hl = & following uncompressed block -; -; uses : af, bc, de, hl - -_zx7_Decompress: - pop bc - pop de - pop hl - push hl - push de - push bc - - ld a, 128 - -zx7t_copy_byte_loop: - - ldi ; copy literal byte - -zx7t_main_loop: - - add a, a ; check next bit - call z, zx7t_load_bits ; no more bits left? - jr nc, zx7t_copy_byte_loop ; next bit indicates either literal or sequence - -; determine number of bits used for length (Elias gamma coding) - - push de - ld de, 0 - ld bc, 1 - -zx7t_len_size_loop: - - inc d - add a, a ; check next bit - call z, zx7t_load_bits ; no more bits left? - jr nc, zx7t_len_size_loop - jp zx7t_len_value_start - -; determine length - -zx7t_len_value_loop: - - add a, a ; check next bit - call z, zx7t_load_bits ; no more bits left? - rl c - rl b - jr c, zx7t_exit ; check end marker - -zx7t_len_value_start: - - dec d - jr nz, zx7t_len_value_loop - inc bc ; adjust length - -; determine offset - - ld e, (hl) ; load offset flag (1 bit) + offset value (7 bits) - inc hl - - sla e - inc e - - jr nc, zx7t_offset_end ; if offset flag is set, load 4 extra bits - add a, a ; check next bit - call z, zx7t_load_bits ; no more bits left? - rl d ; insert first bit into D - add a, a ; check next bit - call z, zx7t_load_bits ; no more bits left? - rl d ; insert second bit into D - add a, a ; check next bit - call z, zx7t_load_bits ; no more bits left? - rl d ; insert third bit into D - add a, a ; check next bit - call z, zx7t_load_bits ; no more bits left? - ccf - jr c, zx7t_offset_end - inc d ; equivalent to adding 128 to DE - -zx7t_offset_end: - - rr e ; insert inverted fourth bit into E - -; copy previous sequence - - ex (sp), hl ; store source, restore destination - push hl ; store destination - sbc hl, de ; HL = destination - offset - 1 - pop de ; DE = destination - ldir - -zx7t_exit: - - pop hl ; restore source address (compressed data) - jp nc, zx7t_main_loop - -zx7t_load_bits: - - ld a, (hl) ; load another group of 8 bits - inc hl - rla - ret - - - end +; ---
+; void zx7_Decompress(void *dest, void *src)
+; ---
+; Dec 2012 by Einar Saukas & Urusergi
+; "Turbo" version (89 bytes, 25% faster)
+; ---
+
+ .def _zx7_Decompress
+ .assume adl=1
+
+; enter : hl = void *src
+; de = void *dst
+;
+; exit : hl = & following uncompressed block
+;
+; uses : af, bc, de, hl
+
+_zx7_Decompress:
+ pop bc
+ pop de
+ pop hl
+ push hl
+ push de
+ push bc
+
+ ld a, 128
+
+zx7t_copy_byte_loop:
+
+ ldi ; copy literal byte
+
+zx7t_main_loop:
+
+ add a, a ; check next bit
+ call z, zx7t_load_bits ; no more bits left?
+ jr nc, zx7t_copy_byte_loop ; next bit indicates either literal or sequence
+
+; determine number of bits used for length (Elias gamma coding)
+
+ push de
+ ld de, 0
+ ld bc, 1
+
+zx7t_len_size_loop:
+
+ inc d
+ add a, a ; check next bit
+ call z, zx7t_load_bits ; no more bits left?
+ jr nc, zx7t_len_size_loop
+ jp zx7t_len_value_start
+
+; determine length
+
+zx7t_len_value_loop:
+
+ add a, a ; check next bit
+ call z, zx7t_load_bits ; no more bits left?
+ rl c
+ rl b
+ jr c, zx7t_exit ; check end marker
+
+zx7t_len_value_start:
+
+ dec d
+ jr nz, zx7t_len_value_loop
+ inc bc ; adjust length
+
+; determine offset
+
+ ld e, (hl) ; load offset flag (1 bit) + offset value (7 bits)
+ inc hl
+
+ sla e
+ inc e
+
+ jr nc, zx7t_offset_end ; if offset flag is set, load 4 extra bits
+ add a, a ; check next bit
+ call z, zx7t_load_bits ; no more bits left?
+ rl d ; insert first bit into D
+ add a, a ; check next bit
+ call z, zx7t_load_bits ; no more bits left?
+ rl d ; insert second bit into D
+ add a, a ; check next bit
+ call z, zx7t_load_bits ; no more bits left?
+ rl d ; insert third bit into D
+ add a, a ; check next bit
+ call z, zx7t_load_bits ; no more bits left?
+ ccf
+ jr c, zx7t_offset_end
+ inc d ; equivalent to adding 128 to DE
+
+zx7t_offset_end:
+
+ rr e ; insert inverted fourth bit into E
+
+; copy previous sequence
+
+ ex (sp), hl ; store source, restore destination
+ push hl ; store destination
+ sbc hl, de ; HL = destination - offset - 1
+ pop de ; DE = destination
+ ldir
+
+zx7t_exit:
+
+ pop hl ; restore source address (compressed data)
+ jp nc, zx7t_main_loop
+
+zx7t_load_bits:
+
+ ld a, (hl) ; load another group of 8 bits
+ inc hl
+ rla
+ ret
+
+
+ end
|