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; (c) Copyright 2007-2008 Zilog, Inc.
;-------------------------------------------------------------------------
; CASE branch resolution.
;
; Input:
; Operand3:
; hl : 24 bit value to match in table
;
; Output:
; Result: hl : 24 bit address of case jp to take
; Registers Used:
;
;-------------------------------------------------------------------------
.def __case8D
.assume adl=1
__case8D equ 000128h
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