blob: f16bb9815ea8b0ea413e80e58e65502fd86fa091 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
|
; (c) Copyright 2001-2008 Zilog, Inc.
;-------------------------------------------------------------------------
; Short Multiply Signed
; Input:
; Operand1:
; bc : 16 bits
;
; Operand2:
; hl : 16 bits
;
; Output:
; Result: hl : 16 bits
;
; Registers Used:
;
;-------------------------------------------------------------------------
.def __smuls
.assume adl=1
__smuls equ 000224h
|