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; (c) Copyright 2001-2008 Zilog, Inc.
;-------------------------------------------------------------------------
; Short NEG.
; Input:
; Operand1:
; hl : 16 bit
;
; Output:
; Result: hl : 16 bit
; Registers Used:
; None
;-------------------------------------------------------------------------
.def __sneg
.assume adl=1
__sneg equ 00022Ch
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