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; (c) Copyright 2001-2008 Zilog, Inc.
;-------------------------------------------------------------------------
; Short Modulus Unsigned
; Input:
; Operand1:
; hl : 16 bits
;
; Operand2:
; bc : 16 bits
;
; Output:
; Result: hl : 16 bits
;
; Registers Used:
; none
;-------------------------------------------------------------------------
.def __sremu
.ref __iremu
.assume adl=1
__sremu equ 00023Ch
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